• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12C
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• pp.727-737
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• 2011

This paper presents an implementation scheme of real-time lane and vehicle detection system with FPGA and DSP. In this type of implementation, defining the functionality of each device in efficient manner is of crucial importance. The FPGA is in charge of extracting features from input image sequences in reduced form, and the features are provided to the DSP so that tracking lanes and vehicles are performed based on them. In addition, a way of seamless interconnection between those devices is presented. The experimental results show that the system is able to process at least 15 frames per second for video image sequences with size of $640{\times}480$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.424-434
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• 2015

Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1119-1128
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• 2001

본 논문에서는 이차원(2-D) 이산 웨이블릿 면환(Discrete Wavelet Transform, DWT)을 이용한 연상압축기를 FPGA 칩에서 실시간으로 동작 가능하도록 하는 효율적인 메모리 스케줄링 방법(E$^2$M$^2$)을 제안하였다. S/W적으로 위의 메모리 사상 방법을 검증한 후, 실제로 상용화된 SFRAM을 선정하여 메모리 제어기를 구현하였다. 본 논문에서는 Mallet-tree를 이용한 2-D DWT 영상압축 칩을 구현할 경우를 가정하였다. 이 알고리즘은 연산 과정에서 많은 데이터를 정장하여야 하는데, FPGA는 많은 데이터를 저장할 수 있는 메모리가 내장되어 있지 않으므로 외부 메모리를 사용하여야 한다. 외부메모리는 열(row)에 대해서만 연속(burst) 읽기, 쓰기 동작이 가능하기 때문에 Mallet-tree 알고리즘의 데이터 입출력을 그대로 적용할 경우 실시간 동작을 수행하는 DWT 압축 칩을 구현할 수 없다. 본 논문에서는 데이터 쓰기를 수행할 경우에는 메모리 셀(cell)의 수직 방향을 저장시키고 읽기를 수행할 때는 수평으로 데이터의 연속 읽기를 수행함으로써 필터가 항상 수평 방향에 위치하게 하는 방법을 제안하였다. 입방법을 C-언어로 DWT 커넬(Kernel)과 메모리의 에뮬레이터(emulator)를 구현하여 실험한 결과, Mallat-tree 이론을 그대로 적용시켰을 때와 동일한 필터링을 수행할 수 있음을 검증하였다. 또한, 상용화된 SDRAM의 메모리 제어기를 H/W로 구현하여 시뮬레이션 함으로써 본 논문에서 제안한 방법이 실제적인 하드웨어로 실시간 동작을 할 수 있음을 보였다.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2678-2680
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• 2003

본 논문에서는 sliding-DFT의 순환구현을 기반한 실시간 위상 측정 앨고리즘을 제시하였다. 종래의 순환형 SDFT 기반 위상 측정 기법은 단일 계수를 사용하기 때문에 계수 근사가 적용되는 하드웨어 구현시 심각한 오차 파급 특성을 나타낸다. 본 논문에서는 순환 구조이면서 회전 위상을 보정을 통해 N-point DFT의 N개의 모든 계수를 적용한 위상 측정 기법을 제시하였고, FPGA 등 하드웨어 구현에 있어서 계수의 유한 비트 근사에 따르는 성능 열화를 해석하였다. 제안한 위상측정 앨고리즘은 실시간 다채널 위상 측정이 가능하도록 FPGA에 구현하였고 동작을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.322-325
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• 2011

스테레오 비전 시스템에서 전통적인 매칭 알고리즘으로 SAD(Sum of Absolute Differences), SSD(Sum of Squared Differences), NCC(Normalized Cross Correlation) 등 다양한 알고리즘이 존재한다. 그러나 하드웨어로 실시간 처리를 위한 시스템을 구현하기 위해서는 리소스가 한정 되어있다는 제약 때문에 많은 연구에서 SAD 혹은 RT(Rank Transform), CT(Census Transform)를 많이 사용하게 된다. FPGA 내부에는 BRAM(Block RAM)과 MAC(multiply-accumulator)인 DSP슬라이스가 이미 존재한다. 본 논문에서는 BRAM과 DSP로직을 활용해서 전통적인 매칭 알고리즘 중에서 연산기 사용이 가장 많은 NCC를 FPGA로 실시간 처리 가능한 하드웨어 구조를 제안한다.

• Journal of IKEEE
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• v.21 no.4
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• pp.358-367
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• 2017

Advanced Driver Assistance Systems(ADAS), such as Front Collision Warning System (FCWS) are currently being developed. FCWS require high processing speed because it must operate in real time while driving. In addition, a low-power system is required to operate in an automobile embedded system. In this paper, FCWS is implemented in CPU-FPGA architecture in embedded system to enable real-time processing. The lane detection enabled the use of the Inverse Transform Perspective (IPM) and sliding window methods to operate at fast speed. To detect the vehicle, a Convolutional Neural Network (CNN) with high recognition rate and accelerated by parallel processing in FPGA is used. The proposed architecture was verified using Intel FPGA Cyclone V SoC(System on Chip) with ARM-Core A9 which operates in low power and on-board FPGA. The performance of FCWS in HD resolution is 44FPS, which is real time, and energy efficiency is about 3.33 times higher than that of high performance PC enviroment.

• Journal of IKEEE
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• v.22 no.3
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• pp.700-705
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• 2018

In this paper, we propose the gas classifier based on restricted column energy neural network (RCE-NN) and present its hardware implementation results for real-time learning and classification. Since RCE-NN has a flexible network architecture with real-time learning process, it is suitable for gas classification applications. The proposed gas classifier showed 99.2% classification accuracy for the UCI gas dataset and was implemented with 26,702 logic elements with Intel-Altera cyclone IV FPGA. In addition, it was verified with FPGA test system at an operating frequency of 63MHz.

• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.792-802
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• 2016

Real time verification is necessary, since there are several features that cannot be verified through design simulation in the design of multiband soundbar system. And then this paper describes an implementation of an FPGA-based real-time verification system for a soundbar SoC with an embedded processor. It is verified a real-time performance test and a listening test which are several features in the design stage that cannot be verified through a design simulation. The measurement of quantitative specifications such as SNR, THD+N, frequency response, etc. as well as the listening test were performed through the implemented FPGA system, and it was verified that test results satisfied the target specifications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2363-2369
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• 2014

The DVR system supports multiple cameras and should be able to receive images at 30 frames per channel in real time. Thus, The system is using Full-HD-grade Multiplexer and Hardware compression codec. In this paper, Describing the design and implementation for the 4-channel Full-HD-grade PC-based DVR using FPGA and GPU inside CPU without Multiplexer and Hardware codec. The existing DVR system for Full-HD-grade has drawbacks to acquire images of about only 20 frames per channel in real time. The system to acquire images of multiple channel in real time was designed using FPGA. The software for the system was implemented using Intel Media SDK. At the result of performance evaluation, It was satisfied all for the required conditions. The practicality of the system was confirmed as implementation the system without using hardware compression.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.813-819
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• 2008

In this paper, we implemented a real-time system which displays 3-dimensional (3D) stereoscopic image with stereo camera. The system consists of a set of stereo camera, FPGA board, and 3D stereoscopic LCD. Two CMOS image sensor were used for the stereo camera. FPGA which processes video data was designed with Verilog-HDL, and it can accommodate various resolutional videos. The stereoscopic image is configured by two methods which are side-by-side and up-down image configuration. After the left and right images are converted to the type for the stereoscopic display, they are stored into SDRAM. When the next frame is inputted into FPGA from two CMOS image sensors, the previous video data is output to the DA converter for displaying it. From this pipeline operation, the real-time operation is possible. After the proposed system was implemented into hardware, we verified that it operated exactly.