• Journal of Institute of Control, Robotics and Systems
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• v.10 no.10
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• pp.922-929
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• 2004

In this paper, we develop control hardware such as an FPGA based general purposed intelligent controller with a DSP board to solve nonlinear system control problems. PID control algorithms are implemented in an FPGA and neural network control algorithms are implemented in a BSP board. An FPGA was programmed with VHDL to achieve high performance and flexibility. The additional hardware such as an encoder counter and a PWM generator can be implemented in a single FPGA device. As a result, the noise and power dissipation problems can be minimized and the cost effectiveness can be achieved. To show the performance of the developed controller, it was tested fur nonlinear systems such as a robot hand and an inverted pendulum.

• The Magazine of the IEIE
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• v.23 no.11
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• pp.23-33
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• 1996

본 논문은 원판과 전용 CAD 틀로 구성되는 FPGA시스템을 개발하는데 있어서 서로 다른 요소 기술들의 관계와 이들 요소 기술들과 시스템성능의 관계를 모델하여 시스템 사양을 만족하기 위하여 가장 효율적인 방법을 찾게하는 방법에 관한 것이다. 본 논문에서는 실제로 개발된 시스템을 예로 하여 FPGA시스템 개발에서 고려해야 할 점들을 고찰하였다. 새로운 FPGA 시스템의 개발 순서는 먼저 개발할 FPGA의 응용 분야를 결정하고, 그 응용 분야에 필요한 시스템 사양에 맞게 개발한 요소 기술들과 그 기술들의 범위를 정한다. 개발 흐름도를 이용하여 이 요소 기술들의 연관 관계를 수직적으로는 시스템 성능에 미치는 영향을 모델링하고 수평적으로는 요소 기술간의 서로 미치는 영향을 모델링 하여 시스템 사양을 만족하기 위한 최적의 해를 구한다. 이때 최종적인 FPGA 시스템을 평가하고 검증할 수 있는 방법을 결정한다. 요소 기술들이 개발 됨에 따라 좀 더 구체적이고 정확한 모델에 의해 전체 시스템의 성능은 평가되고 검증될 수 있다. 이러한 방법과 환경은 FPGA 시스템을 빠르고 효율적으로 개발할 수 있게 한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.675-676
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• 2012

In this paper, we are implemented the signal measurement system based on FPGA. The proposed hardware was mapped into Cyclone III from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.20-27
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• 2008

In this paper, a nonlinear classifier of a feed-forward neural network is implemented on an FPGA chip. The feedforward neural network is implemented in hardware for fast parallel processing. After off line training of neural network, weight values are saved and used to perform forward propagation of neural processing. As an example, AND and XOR digital logic classification is conducted in off line, and then weight values are used in neural network. Experiments are conducted successfully and confirmed that the FPGA neural network hardware works well.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.167-169
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• 2010

This paper describes hardware design and FPGA verification of TFT-LCD controller used in mobile devices widely. TFT-LCD controller outputs pixel's color information red, green, blue and Hsync, Vsync synchronization signals. We used verilog-hdl to describe TFT-LCD controller and simulated it using modelsim software and verified it's exact operation on Xilinx FPGA. Framebuffer made up Block RAM form in FPGA and TFT-LCD displayed image file.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.141-146
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• 2007

In this paper, we proposed an efficient FPGA-based simulation acceleration method based on FPGA compilation avoidance, which can effectively decrease the long debugging turnaround time incurred from the every debugging process in the functional verification. The proposed method had been experimentally applied to the functional verification for a microcontroller design. It had clearly shown that the debugging turnaround time was greatly reduced while the high simulation speed of the simulation acceleration was still maintained.

• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.405-408
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• 2004

본 논문에서는 FPGA와 마이크로프로세서를 이용하여 One Board화된 무선 콘트롤러 시스템의 기저대역부를 설계 하였다. 송신부에서는 컴퓨터와 연결된 마이크로프로세서부에서 컴퓨터를 통해 입력된 데이터를 병렬로 FPGA부로 전송하여 PN_code를 이용한 대역확산 거쳐 전송하고, 수신부에서는 대역역확산를 사용하여 데이터를 다시 수신측 마이크로프로세서를 통해 확인하였다. FPGA 설계는 Xilinx사의 FPGA 디자인 툴인 Xilinx Foundation3.1을 사용하였으며, FPGA configuration을 위한 타이밍 시뮬레이션을 수행하였고. Xilinx사의 SPARTAN2 2S100PQ208칩에 downloading 한 후 Agilent사의 1681A logic analyzer를 사용하여 설계된 회로의 동작을 확인 하였다. 또한 데이터의 입출력을 CPU부를 통해 컴퓨터에서 모니터링 할 수 있도록 설계하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.595-598
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• 2014

원전 디지털 계측제어시스템에서 공통원인고장(Common cause failure)의 발생 가능성이 증가함에 따라 이를 방지하기 위해 프로그래머블 논리소자(Field Programmable Gate Array)를 이용한 제어기가 개발되어 활용되고 있다. 그러나, FPGA-기반의 제어기를 구현하는데 사용되는 하드웨어 기술 언어는 그래픽 언어를 이용한 PLC 기반의 개발을 하던 대부분의 원전 계측제어 엔지니어에게 친숙하지 않아 제어기의 구현에 어려움이 있다. 따라서 엔지니어에게 친숙한 그래픽 언어를 이용하여 FPGA 용 제어 프로그램을 작성할 수 있는 통합개발환경이 필요하다. 본 논문에서 구현한 VerilogLinker 는 제어프로그램의 개발을 위한 통합개발환경의 일부로 통합개발환경을 이용한 제어 프로그램의 개발과정 중에서 생성된 Verilog 파일을 FPGA 공급자가 제공하는 상용 소프트웨어인 Libero SoC 와 연결하는 기능을 제공한다.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.18-27
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• 2010

This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.