• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.4
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• pp.508-514
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• 2020

To implement the continuously evolving mobile communication standards such as Long Term Evolution (LTE) and 5G, the Software Defined Radio (SDR) concept provides great flexibility and efficiency. For many years, a high-end Digital Signal Processor (DSP) System on Chip (SoC) has been developed to support multicore and various hardware coprocessors. This paper introduces the implementation of the SDR platform hardware using TI's TCI663x chip. Using the platform, LTE transport channel is implemented by interworking multicore DSP with Bit rate Coprocessor (BCP) and Turbo Decoder Coprocessor (TCP) and the performance is evaluated according to various implementation options. In order to evaluate the performance of the implemented LTE transport channel, LTE base station system was constructed by combining FPGA main board for physical channels, SDR platform board, and RF & Antenna board.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.2
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• pp.27-33
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• 2022

The small infrared image homing sensor is the eye of a guided weapon that has an infrared image sensor that identifies a target on the ground through day and night infrared image processing and searches, detects, and tracks the target. Inside the guided weapon since the power supply and communication line are used together with various components, the part against electromagnetic wave interference is very important. In particular, the effect of CE (Conducted Emission) through the power and communication lines connected by cables is very important. Through this method, it is possible to directly affect other components of the guided weapon. In this paper, the EMI filter and cable design for avoiding electromagnetic interference to the power input through the cable and the communication line are described. Also, the designed EMI filter is manufactured After the CE102 test of MIL-STD-461G, design satisfaction will be explained.

• Journal of Aerospace System Engineering
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• v.16 no.4
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• pp.10-16
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• 2022

Since aviation systems are developed as the complex form of software a hardware, the necessity to apply to relevant guidelines is increasing. It is however uncommon that international development guidelines regarding electronic hardware are applied to current domestic aviation systems. In this paper, we compare and analyze DO-254 and ECSS-Q-ST-60-02C, electronic hardware development guidelines with the case of KASS (Korea Augmentation Satellite System) Performance Suitability, based on the project of SBAS (Satellite Based Augmentation System) development and construction.

• Journal of Advanced Information Technology and Convergence
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• v.10 no.1
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• pp.71-83
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• 2020

In this paper, we propose a system that can detect the shape of a hand at high speed using an FPGA. The hand-shape detection system is designed using Verilog HDL, a hardware language that can process in parallel instead of sequentially running C++ because real-time processing is important. There are several methods for hand gesture recognition, but the image processing method is used. Since the human eye is sensitive to brightness, the YCbCr color model was selected among various color expression methods to obtain a result that is less affected by lighting. For the CbCr elements, only the components corresponding to the skin color are filtered out from the input image by utilizing the restriction conditions. In order to increase the speed of object recognition, a median filter that removes noise present in the input image is used, and this filter is designed to allow comparison of values and extraction of intermediate values at the same time to reduce the amount of computation. For parallel processing, it is designed to locate the centerline of the hand during scanning and sorting the stored data. The line with the highest count is selected as the center line of the hand, and the size of the hand is determined based on the count, and the hand and arm parts are separated. The designed hardware circuit satisfied the target operating frequency and the number of gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• Journal of IKEEE
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• v.27 no.4
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• pp.624-629
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• 2023

Estimation of signal parameters via rotational invariance techniques (ESPRIT) is an algorithm that estimates the angle of a signal arriving at an array antenna using the shift invariance property of an array antenna. ESPRIT offers the good trade-off between performance and complexity. However, the ESPRIT algorithm still requires high-complexity operations such as covariance matrix and eigenvalue decomposition, so implementation with a hardware processor is essential to estimate the angle of arrival in real time. In addition, ESPRIT processors should have high performance. The performance is related to the number of antennas, and the number of antennas required for each application are different. Therefore, we proposed an ESPRIT processor that provides 2 to 8 variable antenna configurations to meet the performance and complexity requirements according to the applied field. The proposed ESPRIT processor was designed using the Verilog-HDL and implemented on a field programmable gate array (FPGA).

• Nuclear Engineering and Technology
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• v.56 no.2
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• pp.745-752
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• 2024

A method for gamma/neutron event classification based on frequency-domain analysis for mixed radiation environments is proposed. In contrast to the traditional charge comparison method for pulse-shape discrimination, which requires baseline removal and pulse alignment, our method does not need any preprocessing of the digitized data, apart from removing saturated traces in sporadic pile-up scenarios. It also features the identification of neutron events in the detector's full energy range with a single device, from thermal neutrons to fast neutrons, including low-energy pulses, and still provides a superior figure-of-merit for classification. The proposed frequency-domain analysis consists of computing the fast Fourier transform of a triggered trace and integrating it through a simplified version of the transform magnitude components that distinguish the neutron features from those of the gamma photons. Owing to this simplification, the proposed method may be easily ported to a real-time embedded deployment based on Field-Programmable Gate Arrays or Digital Signal Processors. We target an off-the-shelf detector based on a small CLYC (Cs2LiYCl6:Ce) crystal coupled to a silicon photomultiplier with an integrated bias and preamplifier, aiming at lightweight embedded mixed radiation monitors and dosimeter applications.

• Journal of Advanced Navigation Technology
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• v.28 no.2
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• pp.216-224
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• 2024

This paper presents a method for analyzing the reliability of hardware electronic equipment, taking into account failures caused by radiation. Traditional reliability analysis primarily focuses on the wear out failure rate and often neglects the impact of radiation failure rates. We calculate the wear out failure rate through physics of failure analysis, while the radiation failure rate is semi-empirically estimated using the Verilog Fault Injection tool. Our approach aims to ensure reliability early in the development process, potentially reducing development time and costs by identifying circuit vulnerabilities in advance. As an illustrative example, we conducted a reliability analysis on the ISCAS85 circuit. Our results demonstrate the effectiveness of our method compared to traditional reliability analysis tools. This thorough analysis is crucial for ensuring the reliability of FPGAs in environments with high radiation exposure, such as in aviation and space applications.

• The Korean Journal of Nuclear Medicine
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• v.38 no.5
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• pp.338-343
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• 2004

Purpose: The purpose of this study was to develop a small animal PET using dual layer phoswich detector to minimize parallax error that degrades spatial resolution at the outer part of field-of-view (FOV). Materials and Methods: A simulation tool GATE (Geant4 Application for Tomographic Emission) was used to derive optimal parameters of small PET, and PET was developed employing the parameters. Lutetium Oxyorthosilicate (LSO) and Lutetium-Yttrium Aluminate-Perovskite(LuYAP) was used to construct dual layer phoswitch crystal. $8{\times}8$ arrays of LSO and LuYAP pixels, $2mm{\times}2mm{\times}8mm$ in size, were coupled to a 64-channel position sensitive photomultiplier tube. The system consisted of 16 detector modules arranged to one ring configuration (ring inner diameter 10 cm, FOV of 8 cm). The data from phoswich detector modules were fed into an ADC board in the data acquisition and preprocessing PC via sockets, decoder block, FPGA board, and bus board. These were linked to the master PC that stored the events data on hard disk. Results: In a preliminary test of the system, reconstructed images were obtained by using a pair of detectors and sensitivity and spatial resolution were measured. Spatial resolution was 2.3 mm FWHM and sensitivity was 10.9 $cps/{\mu}Ci$ at the center of FOV. Conclusion: The radioactivity distribution patterns were accurately represented in sinograms and images obtained by PET with a pair of detectors. These preliminary results indicate that it is promising to develop a high performance small animal PET.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.