• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.6
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• pp.556-563
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• 2007

The current trend of low cost ultra-small satellites is to utilize Commercial Off the Shelf (COTS) parts to save cost, and accordingly, Command and Data Handling (C&DH) that operates the satellite and collects/processes the data is also designed and developed around commercial controllers. However, functionalities of commercial controllers are limited according to the specs outlined by the manufacturer. In order for the commercial controllers to be used for satellites where variety of interfaces is required, a separate interface circuit is required. Therefore, a Multi Digital Data Control System (MDDCS) using Field Programmable Gate Array (FPGA) has been developed in order to expand multiple digital interfaces that are not supported by the commercial controller, and also to compensate for SEU. This has been implemented on Actel A3P1000 using Very High Speed Integrated Circuits Hardware Description Language (VHDL).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2373-2379
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• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.57-64
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• 2009

This paper presents the hardware implementation of the pyramidal KLT(Kanade-Lucas-Tomasi) feature tracker. Because of its high computational complexity, it is not easy to implement a real-time KLT feature tracker using general-purpose processors. A hardware implementation of the pyramidal KLT feature tracker using FPGA(Field Programmable Gate Array) is described in this paper with emphasis on 1) adaptive adjustment of threshold in feature extraction under diverse lighting conditions, and 2) modification of the tracking algorithm to accomodate parallel processing and to overcome memory constraints such as capacity and bandwidth limitation. The effectiveness of the implementation was evaluated over ones produced by its software implementation. The throughput of the FPGA-based tracker was 30 frames/sec for video images with size of $720{\times}480$.

• Advances in Energy Research
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• v.1 no.2
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• pp.97-106
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• 2013

This study designs and tests a photovoltaic system with distributed maximum power point tracking (DMPPT) methodology using a field programmable gate array (FPGA) controller. Each solar panel in the distributed PV system is equipped with a newly designed DC/DC converter and the panel's voltage output is regulated by a FPGA controller using PI control. Power from each solar panel on the system is optimized by another controller where the quadratic maximization MPPT algorithm is used to ensure the panel's output power is always maximized. Experiments are carried out at atmospheric insolation with partial shading conditions using 4 amorphous silicon thin film solar panels of 2 different grades fabricated by Chi-Mei Energy. It is found that distributed MPPT requires only 100ms to find the maximum power point of the system. Compared with the traditional centralized PV (CPV) system, the distributed PV (DPV) system harvests more than 4% of solar energy in atmospheric weather condition, and 22% in average under 19% partial shading of one solar panel in the system. Test results for a 1.84 kW rated system composed by 8 poly-Si PV panels using another DC/DC converter design also confirm that the proposed system can be easily implemented into a larger PV power system. Additionally, the use of NI sbRIO-9642 FPGA-based controller is capable of controlling over 16 sets of PV modules, and a number of controllers can cooperate via the network if needed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1424-1433
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• 2007

In this paper, we propose a hardware architecture to generate digital hologram using the modified CGH (Computer Generated Hologram) algorithm for hardware implementation and design to FPGA (Field Programmable Gate Array) platform. After analyzing the CGH algorithm, we propose an architecture of CGH cell which efficiently products digital hologram, and design CGH Kernel from configuring CGH Cell. Finally we implement CGH Processor using CGH Kernel, SDRAM Controller, DMA, etc. Performance of the proposed hardware can be proportionally increased through simply addition of CGH Cell in CGH Kernel, since a CGH Cell has operational independency. The proposed hardware was implemented using XC2VP70 FPGA of Xilinx and was stably operated in 200MHz clock frequency. It take 0.205 second for generating $1,280{\times}1,024$ digital hologram from 3 dimensional object which has 40,000 light sources.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.142-146
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• 2012

Today, the demand for high-speed data communication and mobile communication has exploded. Thus, there is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication with these characteristics consists of a master unit (MU) and a slave unit (SU). However, the digital optical units that are currently commercialized or being developed transmit data without compression. Thus, digital optical communication using these units is restricted by the quantity of optical frames when adding diversity or operating with various combinations of CDMA, WCDMA, WiBro, GSM, LTE, and other mobile communication technologies. This paper suggests the application of a data compression algorithm to a digital signal processor (DSP) chip as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD) of a digital optical unit to add separate optical waves or to transmit complex data without specific changes in design of the optical frame.

• Journal of information and communication convergence engineering
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• v.11 no.3
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• pp.190-198
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• 2013

Recently, one of the most vital advancement in the field of finance is high-performance trading using field-programmable gate array (FPGA). The objective of this paper is to design high-performance Black Scholes option trading system on an FPGA. We implemented an efficient Black Scholes Call Option System IP on an FPGA. The IP may perform 180 million transactions per second after initial latency of 208 clock cycles. The implementation requires the 64-bit IEEE double-precision floatingpoint adder, multiplier, exponent, logarithm, division, and square root IPs. Our experimental results show that the design is highly efficient in terms of frequency and resource utilization, with the maximum frequency of 179 MHz on Altera Stratix V.

• The Journal of the Acoustical Society of Korea
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• v.37 no.4
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• pp.215-222
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• 2018

This paper reports the development and performance evaluation of a backend system for real-time IVUS (Intravascular Ultrasound) imaging. The developed backend system was designed to minimize the amount of logic and memory usage by means of efficient LUTs (Look-up Tables), and it was implemented in a single FPGA (Field Programmable Gate Array) without using external memory. This makes it possible to implement the backend system that is less expensive, smaller, and lighter. The accuracy of the backend system implemented was evaluated by comparing the output of the FPGA with the result computed using a MATLAB program implemented in the same way as the VHDL (VHSIC Hardware Description Language) code. Based on the result of ex-vivo experiment using rabbit artery, the developed backend system was found to be suitable for real-time intravascular ultrasound imaging.