• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1833-1839
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• 2014

In this paper, a systematic demapping algorithm for three-dimensional (3-D) lattice signal constellations is presented. The algorithm consists of decision of an octant, computation of a distance from the origin, and determination of the coordinates of a symbol. Since the algorithm can be extended systematically, it is applicable to the larger lattice constellations. To verify the algorithm, 3-D signal transmission systems with field programmable gate array (FPGA) and $Matlab^{(R)}$ are implemented. And they are exploited to carry out computer simulation. As a result, both hardware and software based systems produce almost the same symbol error rates (SERs) in an additive white Gaussian noise (AWGN) environment. In addition, the hardware based system implemented with an FPGA generates waveforms of 3-D signals and recovers the original binary sequences perfectly. Those results confirm that the algorithm and the implemented 3-D transmission system operate correctly.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.9-14
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• 2019

A small millimeter-wave tracking radar is a pulse-based radar that searches, detects, and tracks a target in real time through a TWS (Track While Scan) method for a traps target on the sea with a large RCS running at low speed. It is necessary to develop a board equipped with a high-speed CPU to acquire and track target information through LPRF, DBS, and HRR signal processing techniques for a trap target operating various kinds of dexterous objects such as chaff and decoy, We designed a signal processor structure including DFT (Discrete Fourier Transform) module design that can perform real - time FFT operation using FPGA (Field Programmable Gate Array) and verified the signal processor implemented through performance test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.600-602
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• 2021

With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.437-438
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• 2018

본 논문은 디지털 신호에 포함되어 있는 잡음을 효과적으로 제거하기 위한 프로그램 가능한 디지털 필터를 제안한다. 이러한 필터는 Altera사의 FPGA(Field Programmable Gate Array)인 cycloneII EP2C70F89618를 이용하여 구현하였다. 데이터 신호에 포함된 잡음 제거 알고리즘을 바탕으로 한 출력 영상 신호 결과로부터 알 수 있듯이 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 다양한 잡음에 대해 잡음이 제거된 출력 영상 특성을 보임을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.469-471
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• 2019

본 논문은 신호에 포함되어 있는 다양한 잡음을 효과적으로 제거할 수 있는 프로그램 가능한 디지털 유한 임펄스 응답 필터를 제안한다. 이러한 필터는 복잡도 등을 고려하여 3차 회로로 설계되어 있다. Altera사의 FPGA(Field Programmable Gate Array)인 cyclone II EP2C70F89618를 이용하여 설계하였다. 신호에 포함된 미세하고 다양한 잡음을 제거하기 위한 알고리즘을 개발하였다. 이를 바탕으로 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 다양한 잡음에 대해 우수한 출력 영상을 확인하였다.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1254-1258
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• 2004

This paper presents of position control of Permanent Magnet Synchronous Motor (PMSM) the implementation with Field Programmable Gate Array (FPGA) is proposed. Cascade control with inner loop as a current control and an outer loop as a position control is chosen for simplicity and fast response. FPGA is a single chip (single processing unit), which will perform the following tasks: receive and convert control signal, create a reference current signal, control current and create switch signal and act as position controller in a addition of zero form. The 10 kHz sampling frequency and 25 bit of floating point data are defined in this implementation.The experimental results show that the performance of FPGA based position control is comparable with the hardware based position control, with the advantage of control algorithm flexibility

• International Journal of Control, Automation, and Systems
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• v.1 no.2
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• pp.252-256
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• 2003

A biped robot should be designed to be an effective mechanical structure and have smaller hardware system if it is to be a stand-alone structure. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU, and FPGA as the motor controller. By using FPGA, more flexible hardware system has been achieved, and more compact and simple controller has been designed.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.1
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• pp.54-59
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• 2002

In the three-axis control of satellites by using on-board actuators, gyros are usually used to measure the attitude angles and angular rates. The gyros are operated by electronic parts and mechanical actuators. The digital components of the electronic parts consist of largely FPGA (Field Programmable Gate Array) as one of the methods for VLSI(Very Large Scale Integrated) circuit design, while the mechanical parts provide output signal directly by mechanical actuation of a spinning rotor. In this research, a mixed mode of gyro is implemented in FGA. In addition to the hardware implementation, the simulation study was conducted by using the SABER for the mixed mode simulator. Results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are also presented to validate the FPGA implementation.

• Nuclear Engineering and Technology
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• v.44 no.4
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• pp.363-368
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• 2012

A feedwater controller targeted for an ABWR has been implemented using a modern field programmable gate array (FPGA), and verified using the full scope simulator at Taipower's Lungmen nuclear power station. The adopted control algorithm is a rule-based fuzzy logic. Point to point validation of the FPGA circuit board has been executed using a digital pattern generator. The simulation model of the simulator was employed for verification and validation of the controller design under various plant initial conditions. The transient response and the steady state tracking ability were evaluated and showed satisfactory results. The present work has demonstrated that the FPGA based approach incorporated with a rule-based fuzzy logic control algorithm is a flexible yet feasible approach for feedwater controller design in nuclear power plant applications.

• Advances in robotics research
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• v.2 no.1
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• pp.99-112
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• 2018

The main contribution of this work is the design of a field programmable gate array (FPGA) based ARX-Laguerre proportional-integral observation (PIO) system for fault detection and identification (FDI) in a multi-input, multi-output (MIMO) nonlinear uncertain dynamical robot manipulators. An ARX-Laguerre method was used in this study to dynamic modeling the robot manipulator in the presence of uncertainty and disturbance. To address the challenges of robustness, fault detection, isolation, and estimation the proposed FPGA-based PI observer was applied to the ARX-Laguerre robot model. The effectiveness and accuracy of FPGA based ARX-Laguerre PIO was tested by first three degrees of the freedom PUMA robot manipulator, yielding 6.3%, 10.73%, and 4.23%, average performance improvement for three types of faults (e.g., actuator fault, sensor faults, and composite fault), respectively.