• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.7
• /
• pp.540-549
• /
• 2017

A phase frequency detector(PFD) composed of logic circuits is widely used in a phase locked loop(PLL) due to the easy implementation for integrated circuits. A frequency locked loop(FLL) removes the reference oscillator in the PLL, and the resonator serves as a reference oscillator. A frequency detector(FD) is indispensable for the FLL configuration, and a FD, which is usually composed of a mixer is used to build an FLL. In this paper, instead of FD using mixer, a FD is constructed by using 1.175 GHz resonator composed of microstrip and PFD taking the versatility of PFD into consideration. Using the designed FD, FLL oscillating at a frequency of 1.175 GHz is composed. As a result of comparison with the FLL composed of FD using mixer, it was confirmed that the proposed FLL has better phase noise performance than FLL using mixer FD with FLL bandwidth.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.509-510
• /
• 2006

FLL (Frequency Locked Loop) is the core block for high-speed transceiver. It incorporates a PLL for fine locking action, and a coarse controller for coarse locking action. A coarse controller compares frequencies coarsely and is applied to detected frequency difference directly. Compare to conventional FLL, frequency is applied to proposed FLL. Proposed FLL in this paper achieves only 5 cycles for coarse lock and total frequency locking time is 5 times faster than conventional FLL. Thus, proposed FLL is more useful to Ethernet transceiver application that requires high-speed data transfer than conventional FLL. Proposed FLL is based on $0.18{\mu}m$ process.

• Journal of Physiology & Pathology in Korean Medicine
• /
• v.23 no.1
• /
• pp.199-205
• /
• 2009

It is unclear whether Fructus ligustri Lucidi (FLL) extract anti-proliferative effect in human glioma cells. The present study was therefore undertaken to examine the effect of FLL on cell viability and to determine the underlying mechanism in A172 human glioma cells. Cell viability and cell death were estimated by MTT assay and trypan blue exclusion assay, respectively. Apoptosis was measured by Annexin-V binding assay and cell cycle analysis. Activation of kinases and caspase-3 was estimated by Western blot analysis. FLL resulted in apoptotic cell death in a dose- and time-dependent manner. FLL-induced cell death was not associated with reactive oxygen species generation. Western blot analysis showed that FLL treatment caused down-regulation of PI3K/Akt pathway, but not ERK. The PI3K/Akt inhibitor LY984002 sensitized the FLL-induced cell death and overexpression of Akt prevented the cell death. FLL induced caspase-3 activation and the FLL-induced cell death was prevented by caspase inhibitors. These findings indicate that FLL results in a caspase-dependent cell death through a P13K/Akt pathway in human glioma cells. These data suggest that FLL may serve as a potential therapeutic agent for malignant human gliomas.

• Journal of information and communication convergence engineering
• /
• v.7 no.1
• /
• pp.62-65
• /
• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.29 no.10
• /
• pp.773-782
• /
• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.12A
• /
• pp.1217-1224
• /
• 2008

The carrier tracking has to be basically completed for accurate positioning of Galileo satellite system. The FLL for tracking frequency errors is robust to dynamic stress causing changes of propagation time but hardly tracks accurate carrier tracking. The PLL for tracking phase errors provides accurate carrier tracking but is sensitive to dynamic stress and its tracking performance is decreased when high dynamics exist. In this paper, we design the carrier tracking loop with the FLL-assisted PLL loop filter and co-operations of FLL and PLL to achieve accurate carrier tracking in high dynamic stress. we prove the performance of designed carrier tracking loop via simulations.

• Journal of information and communication convergence engineering
• /
• v.8 no.2
• /
• pp.197-200
• /
• 2010

The FLL(frequency locked loop) circuit is used to generate an output signal that tracks an input reference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL is designed to allow the circuit to be fully integrated. In this paper, the temperature stable FLL circuit is designed by using full CMOS transistors. When the temperature is varied from $-20^{\circ}C$ to $70^{\circ}C$, the variation of output frequency is about from -2% to 1.6% from HSPICE simulation results.

• Journal of information and communication convergence engineering
• /
• v.6 no.3
• /
• pp.275-278
• /
• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• Progress in Superconductivity
• /
• v.5 no.1
• /
• pp.55-60
• /
• 2003

We designed and constructed integrated 3-channel flux-locked-loop (FLL) electronic system for the control and readout of high-T$_{c}$ SQUIDs. This system consists of low noise preamplifiers, integrators, interface circuits, and software. FLL operation was carried out with biased signals of 19 KHz modulated current and 150 KHz modulated flux, which are reconstructed as detected signals by preamplifier and demodulator. Computer controlled interface circuits regulate FLL circuit and adjust SQUID parameters to the optimum operating condition. The software regulates interface circuits to make an auto-tuning for the control of SQUIDs, and displays readout data from FLL circuit. 3-channel SQUID electronic system was assembled with 3 FLL-interface circuit boards and a power supply board in the aluminum case of 56 mm ${\times}$ 53 mm${\times}$ 150 mm. Overall noise of the system was around 150 fT/(equation omitted)Hz when measured in the shielded room, 200 fT/(equation omitted)Hz in a weakly shielded room, respectively.y.

• Proceedings of the KIEE Conference
• /
• 2006.07d
• /
• pp.2149-2150
• /
• 2006

FLL 회로는 측정된 신호를 voltage to current converter를 거쳐 feedbak coil에 인가함으로써 외부 자장을 상쇄하여 SQUID의 동작점을 원점으로 회귀시켜 선형 구간을 유지하도록 하는 역할을 한다. FLL회로의 동자 범위와 특성을 분석하기 위해서는 일반적인 time-delayed feedback 회로와 사용된 OP amp의 slew rate, filter 의 amplitude 및 위상 특성, SQUID의 critical current, pickup coil 및 SQUID의 inductance 등 다양한 파라미터를 고려하여야 한다. 이러한 SQUID 회로의 복합적인 특성을 SQUID 에뮬레이터를 사용함으로써 FLL 회로를 손쉽게 설계할 수 있고, 또한 회로의 최적화도 쉽게 이를 수 있다. 또한 초전도에서 동작하는 SQUID 나 자기 차폐실이 없어도 FLL 회로 등을 개발할 수 있기 때문에 생체자기시스템의 개발 초기 단계에 널리 활용될 수 있다. 따라서 이 논문의 목적은 FLL을 포함한 SQUID 제어 회로를 SQUID 센서와 분리하기 위한 방법을 제안하는 것으로 자기적으로 coupling되어 있는 feedback 회로를 회로적으로 addition을 수행하게 함으로써 SQUID와 분리하여 회로의 동작 및 특성을 측정할 수 있다.