• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.417-420
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• 1999

This paper present the architecture and design of FFT processor for the OFDM modulation. The OFDM modulation have a merit that use frequecncy efficiently and robust ISI. It needs FFR to have fast and large number of points. Moreover, this FFT design has pipeline architecture. R2$^2$SDF architecture for FFT processor has more advantage others. Therefore this paper present FFT processor used R2$^2$SDF architecture.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.255-260
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• 1999

This paper shows the design of a high throughput 512-point FFT processor. The performance target of the 512-point FFT processor is to achieve data symbol rate required for OFDM systems. The memory requirement of the 512-point FFT processor is minimized by adopting shuffle memory system. The hardware cost of the 512-point in processor is further reduced by using a complex multiplier with a new strength reduction method.

• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.1
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• pp.37-41
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• 2014

FFT (Fast Fourier Transform) has been widely used in various fields such as image processing, voice processing, physics, astronomy, applied mathematics and so forth. Much research has been conducted due to the importance of the FFT and recently new FFT algorithms using a GPU (Graphics Processing Unit) have been developed for the purpose of much faster processing. In this paper, the new optimal FFT algorithm using the Pease FFT algorithm has been proposed reflecting the hardware configuration of a GPGPU (General Purpose computing of GPU). According to the experiments, the proposed algorithm outperformed by between 3% to 43% compared to the CUFFT algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.192-195
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• 2003

본 논문에서는 FFT(Fast Fourier Transform)를 수행하며 이를 원격지에 전송할 수 있는 원격 모니터링 시스템을 위한 FFT서버 시스템 구축에 대하여 기술하고자 한다. 실시간으로 얻어지는 데이터를 동시에 FFT분석을 하여 이를 원격지에 전송할 수 있다. 그리고 방대한 양의 데이터의 처리와 전송과정에서 발생하는 시간적, 자원적 손실을 줄일 수 있도록 데이터를 선별하여 분석한다. 제안된 시스템은 실시간 계측 데이터에서 의미있는 데이터를 추출하고, FFT를 통해 1차 처리 후 네트워크를 통해 이를 목적지에 전달한다. 이로 인해 네트워크 자원의 보다 효율적인 사용과 감시 대상의 다양한 각도에서의 분석에 도움이 될 것으로 기대한다.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.257-261
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• 2008

The Digital Radio Mondiale (DRM) system is a digital broadcasting standard designed for use in the LF, MF and HF bands of the broadcasting bands below 30 MHz. The system provides both superior audio quality and improved user services / operability compared with existing AM transmissions. In this paper, we propose a variable point Prime Factor FFT design method for Digital Radio Mondiale (DRM) system. Proposed method processes a various size IFFT/FFT of Robustness Mode on DRM standard efficiently by composing Radix-Prime Factor FFT Processing Unit of form similar to Radix-4 by insertion of a variable Prime Factor Twiddle Factor and Garbage data. So, we improved limitation that cannot process 112/176/256/288 FFT of each mode of DRM system with a existent Radix Processor and increase memory size and memory access time for IFFT/FFT processing by software processing in case of implementation with a existent high speed DSP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2227-2232
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• 2007

In this paper, it is presented a Real FFT for the FMCW radar distance measurement with high resolution. The high distance resolution needs the measurement of the accurate beat frequency. To improve the distance resolution, zoom fft, decimation, digital low pass filter and zero padding method are used. The simulation results using the Matlab show ${\pm}5mm$ of distance resolution and the measuring range is up to 35meter.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.05a
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• pp.1029-1030
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• 2008

FFT(Fast Fourier Transform)는 디지털신호처리에 폭넓게 사용되며 특히 여러 OFDM 시스템에 FFT 처리 과정은 꼭 필요한 부분이다. 본 논문에서는 802.11a W-LAN 에 사용되는 64-point FFT 프로세서를 설계하였다. 설계된 FFT 프로세서는 Radix-$2^3$ 알고리즘을 사용하였으며 저면적복소곱셈기를 사용하여 FFT 프로세서의 면적을 줄이는 방법을 제안한다. 기존의 방식에서 네 개의 실수 곱셈기와 두 개의 덧셈기로 구성되는 복소 곱셈기를 두 개의 실수 곱셈기와 한 개의 덧셈기가 수행하도록 설계하였다. 제안한 FFT 프로세서는 VHDL 로 구현되었고 Quartus 4.2 에서 합성되었다. 합성결과 기존 방식에 비해 약 21%의 면적효율이 발생하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.15-23
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• 2009

This paper presents a novel high-speed, low-complexity flexible 128/64-point $radix-2^4$ FFT/IFFT processor for the applications in high-throughput MIMO-OFDM systems. The high radix multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/IFFT in 128-point and 64-point but can also provide a high data processing rate by using a four-parallel data-path scheme. Furthermore, the proposed design has a less hardware complexity compared with traditional 128/64-point FFT/IFFT processors. Our proposed processor has a high throughput rate of up to 560Msample/s at 140MHz while requiring much smaller hardware expenditure satisfying IEEE 802.11n standard requirements.