• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.3-9
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• 1999

This paper concerns performance of a parallel digital signal processing system. The performance of the system is analyzed in terms of CPU cycles required for 1024-point FFT computation. The number of cycles is estimated in three different approaches; FFT algorithm-based, assembly level source code-based, and probability-based. The results of analysis indicate that on a bus-based system the best performance for FFT is achieved with a single board. Because in some applications like FFT, where frequent data exchanges among processors occur, the number of communication cycles increases as the number of boards. It is observed that inter-board communication degrades overall system performance for the FFT computation. Also shown is that linear increase in performance can be obtained if multiple buses are employed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2121-2126
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• 2013

This paper compares radix-2 based structures for 32768-point FFT. Radix-$2^k$ structures have been widely used because the butterfly is simple and the number of multipliers can be reduced in those structures. This paper applied various radix-$2^k$ structures to 32768-point FFT that is representing ultra-long FFT. The ultra-long FFT has been studied much recently. This paper shows that the radix-$2^4$ structure is the most adequate because it shows the smallest complexity in the synthesis and the best SQNR performance. should be placed here.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.60-64
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• 2007

In this paper, we designed FFT for European DTV and implemented system with Stratix EP1S25F672C6 FPGA At the implemented FFT, we used SIC architecture. SIC architecture is composed of algorithm-specific processing element, RAM memory, registers, and a central or distributed control unit. Designed FFT was acceptable either 2K or 8K point FFT processing, and is selectable guard interval such as 1/4, 1/8, 1/16, 1/32. Consequently, it was suitable for the standard of DVB-T(Digital Terrestrial Video Transmission System) specification. It resulted in 12% of total logic gate and 53% of total memory bit in Stratix device.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.261-269
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• 2004

In this paper, an efficient algorithm for computing in the MPEG/audio Layer Ⅲ (MP3) encoder is proposed. The proposed algerian performs a full-band 1024-point FFT by computing 32-point FFT's of 32 subband outputs. To reduce the aliasing caused by the analysis filter bank, an aliasing cancellation butterfly is developed. A major benefit of the proposed algorithm is the computational saving. By using the proposed algorithm, it is possible to save 40~50% of computations for FFT, which results in about 20% reduction of the PAM-2 complexity.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.157-164
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• 2009

An efficient pipeline MDC Radix-4 FFT structure is proposed in this paper. Every stages in pipeline FFT structure consists of delay' commutator and butterfly. Proposed butterflies in front and rear stages utilize CORDIC and Common Sub-expression Sharing(CSS) techniques, respectively. It is shown that proposed butterfly structure can reduce the number of adders through sharing common patterns of CSD type coefficients. The Verilog-HDL modeling and Synopsys logic synthesis results that the proposed structure show 48.2% cell area reduction in the complex multiplication part and 22.1% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structures. Consequently, the proposed FFT structure can be efficiently used in various OFDM systems.

• Journal of IKEEE
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• v.25 no.4
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• pp.697-702
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• 2021

Fast Fourier Transform (FFT) is a major signal processing block being widely used. For long-point FFT processing, usually more than 1024 points, its low-complexity implementation becomes very important while retaining high SQNR (Signal-to-Quantization Noise Ratio). In this paper, we present a low-complexity FFT algorithm with a simple dynamic scaling scheme. For the 2048-point pipelined FFT processing, we can reduce the number of general multipliers by half compared to the well-known radix-2 algorithm. Also, the table size for twiddle factors is reduced to 35% and 53% compared to the radix-2 and radix-2² algorithms respectively, while achieving SQNR of more than 55dB without increasing the internal wordlength progressively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.1
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• pp.11-19
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• 2024

The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).