• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.11
• /
• pp.140-148
• /
• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.118-119
• /
• 2009

This paper presents the feature profile evolution silicon deep trench etching, which is very crucial for the commercial wafer process application. The silicon deep trenches were etched with the SF6 gas & Hbr gas based process recipe. The optimized silicon deep trench process resulted in vertical profiles (87o~90o) with loading effect of < 1%. The process recipes were developed for the silicon deep trench etching applications. This scheme provides vertically profiles without notching of top corner was observed. In this study, the production of SF6 gas based silicon deep trench etch process much more strongly than expected on the basis of Hbr gas trench process that have been investigated by scanning electron microscope (SEM). Based on the test results, it is concluded that the silicon deep trench etching shows the sufficient profile for practical MOS FET silicon deep trench technology process.

• Membrane and Water Treatment
• /
• v.14 no.3
• /
• pp.141-146
• /
• 2023

Algal organic matters (AOMs) are challenging to remove using traditional water treatment methods. Additionally, they are recognized as disinfection by product (DBP) precursors during the chlorination process. These compounds have the potential to seriously harm aquatic creatures. Despite the fact that AOMs and DBPs formed from algae can harm aquatic species by impairing their cognitive function and causing behavioral problems, only a few studies on the effects of AOMs and associated DBPs have been conducted. To assess the impact of extracellular organic materials (EOMs) produced by three different hazardous algal species and the chlorinated EOMs on zebrafish, this study used fish acute embryo toxicity (FET) and cognitive function tests. With rising EOM concentrations, the embryo's survival rate and mental capacity both declined. Of the three algal species, the embryo exposed to Microcystis aeruginosa EOM exhibited the lowest survival rate. On the other hand, the embryo exposed to EOMs following chlorination demonstrated a drop in CT values in both the survival rate and cognitive ability. These findings imply that EOMs and EOMs treated with chlorine may have detrimental effects on aquatic life. Therefore, an effective EOM management is needed in aquatic environment.

• Proceedings of the Korea Concrete Institute Conference
• /
• 1989.10a
• /
• pp.53-58
• /
• 1989

Thicknesses of the base concrete blocks for large machines were estimated by analyzing the resonance modes of mechanical vibrations. The vibration was produced by the mechanical impact and detected by a wideband conical transcuder. There signals were analyzed by FET and thicknesses were obtained by the peaks of frequency spectrum. The estimated thickness upto 100cm are in good agreement with the real ones. For the layered concrete block, the estimated thickness is dependent on the acoustic reflective index at the boundary of the two layers.

• Journal of Korean Society on Water Environment
• /
• v.28 no.5
• /
• pp.762-767
• /
• 2012

The ecotoxicity assessment of nanomaterials (NMs) in the environment is actively conducted throughout the world because of the concerns about their potential risk from usage and release into the environment, as well as their unique physiochemical properties. Ecotoxicity tests for NMs have been conducted using various species and methods; however, in spite of these efforts, the characteristics and toxicity of NMs have not been defined. The fish embryo toxicity test (FET) has been conducted extensively to evaluate the toxicity of NMs as an alternative to a whole-body test in fish. In this study, we collected and analyzed the trends of nanotoxicity on the early development of freshwater fish. The model nanomaterials are carbon NMs ($C_{60},\;C_{70},\;C_{60}$(OH)n and carbon nanotube). Their adverse effects were extensively investigated based on the properties of NMs, test species, and diverse exposure conditions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.11
• /
• pp.1047-1054
• /
• 2003

Smart battery pack (SBP) for notebook PCs was developed using a cylindrical-type lithium ion battery. Batteries were connected with three serial and two parallel, the nominal capacity and the maximum load of SBP was 4,000mAh and 4.0A, respectively. The SBP was composed of a protection IC, by which safety of lithium ion batteries is maintained against overcharge, overdischarge and overcurrent, and a smart IC, which calculates the remaining capacity and the remaining run time. In matching test on notebook PC using Battery Mark 4.0, real and smart data of END voltage coincided nearly and LB and LLB signal worked norma]]y. And there were errors of less than 1% between the real and the smart data on the residual capacity in the charge and discharge test.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.4
• /
• pp.265-275
• /
• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• Proceedings of the Korean Vacuum Society Conference
• /
• 1999.07a
• /
• pp.87-87
• /
• 1999

본 연구에서는 Pulsed Laser Deposition(이하 PDL)방법을 이용하여 Si기판에 (Ba,Sr)TiO3(이하 BST)박막을 MFS-FET(Metal-Ferroelectric-Semiconductor Field-effect Transistor)구조로 제조하였으며 BST박막의 강유전성이 BST 박막에 유도되는 응력에 어떤 영향을 받는지 살펴보았다. 본 연구에서는 완충막을 사용함으로써 BST박막과 완충막간의 격자부정합을 이용하여 BST박막에 강유전성을 유도하려고 하였다. 또한 MFS-FET구조의 BST박막에 유도되는 응력조절을 위하여 BST박막과 완충막의 두께를 변화하였으며 XRD를 통한 구조 분석 및 C-V test를 통한 전기적 특성을 관찰을 하였다. PLD법을 통해서 epitaxial 성장된 BST 박막에서는 Si에 epitaxial 성장된 완충막과의 격자부정합에 의한 BST박막내의 자발분극의 발생이 예상된다. 따라서, 본 연구는 강유전체의 자발분극에 의하여 발생되는 C-V 이력현상이 BST박막과 완충막과의 격자부정합에 의한 응력에 의해 발생될 것으로 예상하여, BST 박막에 유도되는 응력과 C-V 이력현상의 관계를 통하여 상온에서 상유전성을 갖는 BST가 응력에 의하여 어느 정도의 강유전성을 나타내는지를 밝히기 위해 진행되었다. 본 연구에서 사용된 완충막은 YSZ(Yttria Stabilized Zirconia)박막으로 0.4mTorrO2 분위기 하에서 600~80$0^{\circ}C$의 온도에서 증착하여 상형성을 살펴보았고 $700^{\circ}C$에서 epitaxial 성장을 확인하였으며 두께는 30~$\AA$으로 변화하였다. 또한 BST박막은 완충막과의 전압분배를 고려해 300~2000$\AA$으로 두께를 변화를 시키며 증착하였다. MFS 구조에서 Al 전극을 사용하여 완충막과 BST박막간의 두께 변화에 따른 Capacitance - Voltage(C-V) 측정을 하였으며 이를 통하여 강유전상의 특성인 C-V 이력현상을 관찰하였다. 그 결과 YSZ 박막에서는 C-V 이력현상이 나타나지 않았으며 BST 박막에서는 약 1.2V의 C-V이력현상이 보였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.33 no.3
• /
• pp.169-172
• /
• 2020

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is V_G=V_D, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.

• Proceedings of the KIPE Conference
• /
• 2003.07a
• /
• pp.256-259
• /
• 2003

In this paper describes the development testing results of high density High Voltage Power Supply(HVPS) that employ microwave TWTs. The HVPS consist of number of modules connected in series. A new design that adapt resonant circuit and high density pulse transformer to the high voltage modules makes the HVPS much more reliable. Also High voltage Solid-State modulation using fast switching devices(FET's) and the test results of modulator modules development are represented.