• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.4
• /
• pp.265-275
• /
• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• Journal of Semiconductor Engineering
• /
• v.1 no.1
• /
• pp.38-45
• /
• 2020

With the recent emergence of foldable electronic devices, interest in flexible organic memory is significantly growing. There are three types of flexible organic memory that have been researched so far: floating-gate (FG) memory, ferroelectric field-effect-transistor (FeFET) memory, and resistive memory. Herein, performance parameters and operation mechanisms of each type of memory device are introduced, along with a brief summarization of recent research progress in flexible organic memory.

• Proceedings of the Optical Society of Korea Conference
• /
• 1989.02a
• /
• pp.185-192
• /
• 1989

It is shown that GaAs/GaAs stripe Roof-Top-Reflector LD is better than cleaved mirror LD by numerical analysis. And surface light emitting device is developed by LPE melt-back growth, which is of good controllability for OEIC. OEIC transmitter using RTR LD structured device and FET has been made and modulated, expected to show good modulation characteristics after solving process problem. Beam-Lead LD mounted on Si carrier has been made and shows low heat-resistance and so long life and good characteristics of LD.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.05a
• /
• pp.132-134
• /
• 2000

This paper presents self-oscillating mixer(SOM) with simple structure which includes dc source, a cross type groove, and a three terminal GaAsFET. By using parasitic elements such as cooper wires, If level of the active antenna is increased. In order to include active device into FDTD analysis, equivalent voltage source are used to substitute for the active device and to describe the voltage-current relationships. This approach is applied to analyze SOM theoretically.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.10
• /
• pp.33-46
• /
• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• Proceedings of the Korean Magnestics Society Conference
• /
• 2007.12a
• /
• pp.112-113
• /
• 2007

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.48 no.1
• /
• pp.90-100
• /
• 2011

We present a parallel bi-conjugate gradient (Bi-CG) matrix solver for large scale Bio-FET simulations based on recent graphics processing units (GPUs) which can realize a large-scale parallel processing with very low cost. The proposed method is focused on solving the Poisson equation in a parallel way, which requires massive computational resources in not only semiconductor simulation, but also other various fields including computational fluid dynamics and heat transfer simulations. As a result, our solver is around 30 times faster than those with traditional methods based on single core CPU systems in solving the Possion equation in a 3D FDM (Finite Difference Method) scheme. The proposed method is implemented and tested based on NVIDIA's CUDA (Compute Unified Device Architecture) environment which enables general purpose parallel processing in GPUs. Unlike other similar GPU-based approaches which apply usually 32-bit single-precision floating point arithmetics, we use 64-bit double-precision operations for better convergence. Applications on the CUDA platform are rather easy to implement but very hard to get optimized performances. In this regard, we also discuss the optimization strategy of the proposed method.

• Applied Science and Convergence Technology
• /
• v.26 no.5
• /
• pp.110-113
• /
• 2017

The two-dimensional layered $MoS_2$ has high mobility and excellent optical properties, and there has been much research on the methods for using this for next generation electronics. $MoS_2$ is similar to graphene in that there is comparatively weak bonding through Van der Waals covalent bonding in the substrate-$MoS_2$ and $MoS_2-MoS_2$ heteromaterial as well in the layer-by-layer structure. So, on the monatomic level, $MoS_2$ can easily be exfoliated physically or chemically. During the $MoS_2$ field-effect transistor fabrication process of photolithography, when using water, the water infiltrates into the substrate-$MoS_2$ gap, and leads to the problem of a rapid decline in the material's yield. To solve this problem, an epoxy-based, as opposed to a water-based photoresist, was used in the photolithography process. In this research, a hydrophobic $MoS_2$ field effect transistor (FET) was fabricated on a hydrophilic $SiO_2$ substrate via chemical vapor deposition CVD. To solve the problem of $MoS_2$ exfoliation that occurs in water-based photolithography, a PPMA sacrificial layer and SU-8 2002 were used, and a $MoS_2$ film FET was successfully created. To minimize Ohmic contact resistance, rapid thermal annealing was used, and then electronic properties were measured.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.562-562
• /
• 2012

Recently, graphene and graphene-based materials such as graphene oxide (GO) or reduced graphene oxide (R-GO) draws a great attention for electronic devices due to their structures of one atomic layer of carbon hexagon that have excellent mechanical, electrical, thermal, optical properties and very high specific surface area that can be high potential for chemical functionalization. R-GO is a promising candidate because it can be prepared with low-cost from solution process by chemical oxidation and exfoliation using strong acids and oxidants to produce graphene oxide (GO) and its subsequent reduction. R-GO has been used as semiconductor or conductor materials as well as sensing layer for bio-molecules or ions. In this work, reduced graphene oxide field-effect transistor (R-GO FET) has been fabricated with ITO extended gate structure that has sensing area on ITO extended gate part. R-GO FET device was encapsulated by tetratetracontane (TTC) layer using thermal evaporation. A thermal annealing process was carried out at $140^{\circ}C$ for 4 hours in the same thermal vacuum chamber to remove defects in R-GO film before deposition of TTC at $50^{\circ}C$ with thickness of 200 nm. As a result of this process, R-GO FET device has a very high stability and durability for months to serve as a transducer for sensing applications.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.482-483
• /
• 2011

Graphene is a good candidate for the future nano-electronic materials because it has excellent conductivity, mobility, transparency, flexibility and others. Until now, most graphene researches are focused on the nano electronic device applications, however, biological application of graphene has been relatively less reported. We have fabricated a deoxyribonucleic acid (DNA) conjugated graphene field-effect transistor (FET) and measured the electrical transport characteristics. We have used graphene sheets grown on Ni substrates by chemical vapour deposition. The Raman spectra of graphene sheets indicate high quality and only a few number of layers. The synthesized graphene is transferred on top of the substrate with pre-patterned electrodes by the floating-and-scooping method [1]. Then we applied adhesive tapes on the surface of the graphene to define graphene flakes of a few micron sizes near the electrodes. The current-voltage characteristic of the graphene layer before stripping shows linear zero gate bias conductance and no gate operation. After stripping, the zero gate bias conductance of the device is reduced and clear gate operation is observed. The change of FET characteristics before and after stripping is due to the formation of a micron size graphene flake. After combined with 30 base pairs single-stranded poly(dT) DNA molecules, the conductance and gate operation of the graphene flake FETs become slightly smaller than that of the pristine ones. It is considered that DNA is to be stably binding to the graphene layer due to the ${\pi}-{\pi}$ stacking interaction between nucleic bases and the surface of graphene. And this binding can modulate the electrical transport properties of graphene FETs. We also calculate the field-effect mobility of pristine and DNA conjugated graphene FET devices.