• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.3
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• pp.81-87
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• 2015

In order to effectively protect electrical and electronic circuits which are extremely susceptible to lightning surges, multi-stage surge protection circuits are required. This paper presents the operational characteristics of the two-stage hybrid surge protection circuit in extra-low voltage DC power lines. The hybrid surge protective device consists of the gas discharge tube, transient voltage suppressor, and series inductor. The response characteristics of the proposed hybrid surge protective device to combination waves were investigated. As a result, the proposed two-stage surge protective device to combination wave provides the tight clamping level of less than 50V. The firing of the gas discharge tube to lightning surges depends on the de-coupling inductance and the rate-of-change of the current flowing through the transient voltage suppressor. The coordination between the upstream and downstream components of the hybrid surge protective device was satisfactorily achieved. The inductance of a de-coupler in surge protective circuits for low-voltage DC power lines, relative to a resistance, is sufficiently effective. The voltage drop and power loss due to the proposed surge protective device are ignored during normal operation of the systems.

• ETRI Journal
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• v.30 no.3
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.12
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• pp.1-8
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• 2012

The performance and lighting characteristics of the LED depend on cooling condition because the power LED generates lots of heat. In this paper, the effect of the generated heat from power LED module on lighting characteristics and performance is measured and evaluated. For experiments, the transient temperature of a power LED module with cooling condition is measured. In addition, the temperature and lighting characteristics of the LED module are measured during the steady state. As a result, the cooling condition is less effective on the lighting characteristics of the LED module at rated current but the cooling condition extremely affects those of the LED module over the rated current. Because high temperature of the power LED module causes the low phosphor conversion, luminance efficiency becomes low and color temperature becomes high. When power LED module are driven over the rated condition, higher temperature is directly related to lighting characteristics and performance of the LED module rather than higher current.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1159-1160
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• 2006

As the grid-connected photovoltaic power conditioning systems (PVPCS) are installed in many residential areas, this has raised potential problems of network protection on electrical power system. One of the numerous problems is an Island phenomenon. There has been an argument that because the probability of islanding is extremely low it may be a non-issue in practice. However, there are three counter-arguments: First, the low probability of islanding is based on the assumption of 100% power matching between the PVPCS and the islanded local loads. In fact, an island can be easily formed even without 100% power matching (the power mismatch could be up to 30% if only traditional protections are used, e.g. under/over voltage/frequency). The 30% power-mismatch condition will drastically increase the islanding probability. Second, even with a larger power mismatch, the time for voltage or frequency to deviate sufficient to cause a trip, plus the time required to execute the trip (particularly if conventional switchgear is required to operate), can easily be greater than the typical re-close time on the distribution circuit. And, third, the low-probability argument is based on the study of PVPCS. Especially, if the output power of PVPCS equals to power consumption of local loads, it is very difficult for the PVPCS to sustain the voltage and frequency in an island. Unintentional islanding of PVPCS may result in power-quality issues, interference to grid-protection devices, equipment damage, and even personnel safety hazards. So the verification of anti-islanding performance is strongly needed. In this paper, the authors propose the improved RPV method through considering power quality and anti-islanding capacity of grid-connected three-phase PVPCS in IEEE Std 1547 ("Standard for Interconnecting Distributed Resources to Electric Power Systems"). And the simulation and experimental results are verified.

• Journal of electromagnetic engineering and science
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• v.5 no.1
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• pp.8-13
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• 2005

The InGaP/GaAs hetero-junction bipolar transistor(HBT) monolithic voltage-controlled dielectric resonator oscillator(VCDRO) is first demonstrated for a Ku-band low noise block down-converter(LNB) system. The on-chip voltage control oscillator core employing base-collector(B-C) junction diodes is proposed for simpler frequency tuning and easy fabrication instead of the general off-chip varactor diodes. The fabricated VCDRO achieves a high output power of 6.45 to 5.31 dBm and a wide frequency tuning range of ]65 MHz( 1.53 $\%$) with a low phase noise of below -95dBc/Hz at 100 kHz offset and -115 dBc/Hz at ] MHz offset. A]so, the InGaP/GaAs HBT monolithic DRO with the same topology as the proposed VCDRO is fabricated to verify that the intrinsic low l/f noise of the HBT and the high Q of the DR contribute to the low phase noise performance. The fabricated DRO exhibits an output power of 1.33 dBm, and an extremely low phase noise of -109 dBc/Hz at 100 kHz and -131 dBc/Hz at ] MHz offset from the 10.75 GHz oscillation frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.553-562
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• 2007

In this paper, we designed and implemented the system for telemetering ELF(Extremely Low Frequency) magnetic field intensity. The magnetic field measurement system used a 3-axis magnetic field sensor to measure the magnetic field with isotropy and the equalizer to compensate the frequency characteristic in band. By multiplexing three output signals of the magnetic field sensor in time domain, we got the uniform gain and frequency characteristic among three axes. This system was designed that the magnetic field measurement level range was $0.01{\sim}10.0\;uT$ and the measurement frequency band was $40{\sim}180\;Hz$. The control system would access to the magnetic field measurement system with RF and the maximum access distance was 1.0 km. We confirmed that the measurement level error of the fabricated system was within 5 %. The fabricated system was installed to a golf practice range where a high voltage power transmission line was crossed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1465-1470
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.494-498
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• 2004

In this paper, the design of a CMOS exponential V-I converter (EVIC,) based on Taylor's concept, is presented. The composite NMOS transistor is used for realizing the exponential characteristics. In a 0.25 $\mu$m CMOS process, the simulations show more than 20 dB output current range and 15 dB linear range with the linearity error less than $\pm$ 0.5 dB. The power dissipation is less than 0.3 mW with $\pm$ 1.5 V supply voltage. The proposed EVIC can be used for the design of an extremely low­voltage and low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.5
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• pp.1093-1100
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• 2018

Fast progress in miniaturization and reducing power consumption of semiconductors for wearable devices makes it possible to develop extremely small wearable systems for various application services. This results recent wearable applications to be powered from extremely low-power energy harvesters based on solar, piezo, and TENG sources. In most cases, the harvesters generate power in non-linear manner. Therefore, we implemented and experimented the device platforms to utilize natural frequency of around 3Hz. We also designed two-stage power storages and high efficiency conversion platform to consider such non-linear power harvesting sources. The experiment showed power generation of about 4.67mW/min from these non-linear sources with provision of stable energy storages.