• Journal of Power Electronics
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• v.11 no.5
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• pp.655-661
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• 2011

This paper presents two topologies for single-stage single-phase double-buck type PFC converters, designed to operate at high power factor, near sinusoidal input currents and adjustable output voltage. Unlike the known buck type PFC topologies, in which the output voltage is always lower than the maximum input voltage, the proposed converters can operate at output voltages higher than the ac input peak voltage. A reduced number of switches on the main path of the current are another characteristic of the two proposed topologies. To shape the input line currents, a fast and robust controller based on a sliding mode approach is proposed. This active non-linear control strategy, applied to these converters allows high quality input currents. A Proportional Integral (PI) controller is adopted to regulate the output voltage of the converters. This external voltage controller modulates the amplitude of the sinusoidal input current references. The performances of the presented rectifiers are verified with experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.1-7
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• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.1
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• pp.53-57
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• 2010

This study proposes the algorithm which drives the powerless without battery. The exiting wire or RF type dosimeter, which is the computation of the real time with battery on the dose radiation exposure, In the Wired dosimeter, it is trouble to need the maintenance and management by periods. Besides, the case of the RF typed dosimeter with battery, it is requested to size bigger and to replace battery frequently and so on. Especially RF typed dosimeter has trouble to need for the embody with large power consumption on the contactless typed dosimeter. As the method for the low power, the study designed to be down the operating clock of the MPC, to improve the efficiency of the rectifier, to eliminate the external memory and the DC-DC converter for the simplification of the circuit We convince our research contributes not only to understand the simplified circuit and miniaturization, but also to help the design and application technology of the powerless dosimeter.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1471-1481
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• 2014

This paper presents the new power dissipation model of individual switching device in a high-level modular multilevel converter (MMC), which can be mostly used in voltage sourced converter (VSC) based high-voltage direct current (HVDC) system and flexible AC transmission system (FACTS). Also, the voltage balancing method based on sorting algorithm is newly proposed to advance the MMC functionalities by effectively adjusting switching variations of the sub-module (SM). The proposed power dissipation model does not fully calculate the average power dissipation for numerous switching devices in an arm module. Instead, it estimates the power dissipation of every switching element based on the inherent operational principle of SM in MMC. In other words, the power dissipation is computed in every single switching event by using the polynomial curve fitting model with minimum computational efforts and high accuracy, which are required to manage the large number of SMs. After estimating the value of power dissipation, the thermal condition of every switching element is considered in the case of external disturbance. Then, the arm modeling for high-level MMC and its control scheme is implemented with the electromagnetic transient simulation program. Finally, the case study for applying to the MMC based HVDC system is carried out to select the appropriate insulated-gate bipolar transistor (IGBT) module in a steady-state, as well as to estimate the proper thermal condition of every switching element in a transient state.

• Journal of The Korean Society For Urban Railway
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• v.6 no.4
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• pp.427-436
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• 2018

HADAX is a serial communication converter of train control computer. It is connected with various signal equipments such as wayside signal equipments, station signal equipments, train control computers, and transmits control information and signal condition information for train control. And transmits information to several electronic interlocking devices through a splitter interface. Since HADAX interfaces with many signaling devices through serial communication, frequent communication connection faults necessitate improvement of performance such as dual system configuration, integration of external splitter, and multi-channelization of communication card. The improved HADAX device should have compatibility with the dimensions of existing enclosure and enclosure, and verify the performance of dual system and splitter integration. Therefore, we verified the performance of HADAX through the route control test, dual system test, and multi-channel communication test with splitter integrated connection by connecting with the existing signal equipment.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.617-624
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• 2022

The small electric vehicles equipped with V2X(vehicle to everything) systems may provide more information and function to the existing navigation system of the vehicle. The key components of V2X technology include V2V (vehicle to vehicle), V2N(vehicle to network) and V2I (vehicle to infrastructure). This study is to design and implementation of VI type E-PTO which is interfaced with external equipments, the work designs the components of E-PTO such as DC/DC converter, DC/AC converter, battery bidirectional charging system etc. Also, it implements the devices and control systems for driving. The test results of VI type E-PTO components showed allowable 10% requirements of transient voltage variation rate and recovery time within 100ms for start/stop and normal operation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.6
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• pp.307-315
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• 2003

This paper proposes a novel simulation method of WPGS (Wind Power Generation System). The rotation speed control method of turbine under variable wind speed using the pitch control is proposed. Moreover, when wind speed exceeds the cut-out wind speed, the turbine will be stopped by controlling pitch angle to 90$^{\circ}$, otherwise it will be controlled to steady-state operation. For the purpose of effective simulation, the SWRW (Simulation method for WPGS using Real Weather condition) is used for the utility interactive WPGS simulation in this paper, in which those of three topics for the WPGS simulation: user-friendly method, applicability to grid-connection and the utilization of the real weather conditions, are satisfied. It is impossible to consider the real weather conditions in the WPGS simulation using the EMTP type of simulators and PSPICE, etc. External parameter of the real weather conditions is necessary to ensure the simulation accuracy. The simulation of the WPGS using the real weather conditions including components modeling of wind turbine system is achieved by introducing the interface method of a non-linear external parameter and FORTRAN using PSCAD/EMTDC in this paper. The simulation of long-term, short-term, over cut-out and under cut-out wind speeds will be peformed by the proposed simulation method effectively. The efficiency of wind power generator, power converter and flow of energy are analyzed by wind speed of the long-term simulation. The generator output and current supplied into utility can be obtained by the short-term simulation. Finally, transient-state of the WPGS can be analyzed by the simulation results of over cut-out and under cut-out wind speeds, respectively.

• ETRI Journal
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• v.30 no.5
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.