• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.971-974
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• 2005

In this paper, we describe photonic sensor interface in SOPC(System on a programmable chip) platform. This platform uses device that has ARM922T processor and APEX FPGA area on a chip. We use two development kits. The one is embedded kit that using Intel's Xscale device, the another is SOPC kit that using Altera's Excalibur device. We implement some device logic that DMAC, ADCC, etc. and application.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.687-688
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• 2006

This paper presents implementation of the lifting based DWT processor interface which the process of JPEG2000. The proposed architecture uses Excalibur device produced Altera. This study describes CIS(CMOS Image Sensor), DMA(Direct Memory Access) and DWT control logic

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.665-666
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• 2006

By adding user interface to the usual router, an improved functional router is implemented In this paper, we design the DWT(Discrete Wavelet Transform) for JPEG2000 CODEC. The DWT is developed based on ARM-based Excalibur, and the system contains DMA processor, Slave interface, DWT filter, Controller. The architecture of the prposed DWT is verified using Altera QuartusII.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.203-206
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• 2004

본 논문은 SoC 환경에서 암호화 알고리즘의 처리 성능을 향상시키기 위해 각 노드의 실행 시간을 비교하여 하드웨어와 소프트웨어로 codesign 하였다. 암호화 알고리즘으로서는 DES와 SHA-1을 통합 설계하여 적용하였다. 본 논문에서의 codesign 방법을 altera의 excalibur에서 구현하여 실행 시간 및 메모리 크기 그리고 회로의 게이트 크기를 비교 대상으로 하였다. 수행 결과에 따른 분석에 의하면 세가지 비교 대상에 최적화하여 codesign 성능을 찾을 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.102-111
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• 2005

In this paper, we propose an advanced hardware architecture for the fast inter prediction engine of the video coding standard MPEG-4 AVC. We describe the algorithm and derive the hardware architecture emphasizing and real time operation of the quarter_pel based motion estimation. The fast inter prediction engine is composed of block segmentation, motion estimation, motion compensation, and the fast quarter_pel calculator. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur & Virtex2 FPGA, and also by synthesis on Samsung 0.18 um CMOS technology. The synthesis result shows that the proposed hardware can operate at 62.5MHz. In this case, it can process about 88 QCIF video frames per second. The hardware is being used as a core module when implementing a complete MPEG-4 AVC video encoder chip for real-time multimedia application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.68-73
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• 2008

In this paper, we propose watermark algorithm called TDWA(Time-Division Watermarking Algorithm) and we applied the proposed algorithm to H.264 video coding standard. We establish that a proposed algorithm is applied to H.264 baseline profile CODEC. The proposed algorithm inserts a watermark into the spatial domain of several frames. We can easily insert strong and invisible watermarks into original pictures using this method. For verification of the proposed algorithm we design hardware core using Verilog-HDL and Excalibur for JM 8.7 code with hardware & software co-simulation. As a result of verification, the PSNR between watermarked pictures and original pictures are more than 60dB and we found the watermark is kept more than 80% after encoding of H.264/AVC with quantization parameter of 28 in baseline profile.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.182-184
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• 2009

FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive and ship applications. FlexRay communication controller(CC) is the core of the FlexRay protocol specification. In this paper, we first design the FlexRay CC protocol specification and function parts using SDL(Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay CC system was synthesized using Samsung $0.35{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 80 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with sound source localization system in Robot applications. The combined system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.