• KIPS Transactions on Computer and Communication Systems
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• v.4 no.3
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• pp.85-90
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• 2015

In this paper, anew parallel event-driven logic simulation is proposed. As the proposed prediction-based parallel event-driven simulation method uses both prediction data and actual data for the input and output values of local simulations executed in parallel, the synchronization overhead and the communication overhead, the major bottleneck of the performance improvement, are greatly reduced. Through the experimentation with multiple designs, we have observed the effectiveness of the proposed approach.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.5
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• pp.147-152
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• 2015

In general, there are two synchronization methods in parallel event-driven simulation, pessimistic approach and optimistic approach. In this paper, we propose a new approach, sporadic synchronization combining both for prediction-based parallel event-driven logic simulation. We claim this hybrid solution is pretty effective to minimize both checkpoint overhead and restart overhead, which are related problems with frequent false predictions for improving the performance of the prediction-based parallel event-driven logic simulation. The experiment has clearly shown the advantage of the proposed approach.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.57-64
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• 2019

In this paper, an efficient prediction-based parallel simulation method using spatially partial simulation strategy is proposed for improving both the performance of the event-driven gate-level timing simulation and the debugging efficiency. The proposed method quickly generates the prediction data on-the-fly, but still accurately for the input values and output values of parallel event-driven local simulations by applying the strategy to the simulation at the higher abstraction level. For those six designs which had used for the performance evaluation of the proposed strategy, our method had shown about 3.7x improvement over the most general sequential event-driven gate-level timing simulation, 9.7x improvement over the commercial multi-core based parallel event-driven gate-level timing simulation, and 2.7x improvement over the best of previous prediction-based parallel simulation results, on average.

• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.61-68
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• 1995

The performance of event-driven logic simulation frequently used for VLSI design verification depends on the data structures for event queues. This paper improves the existing Timing Wheel as a data structure for an event queue. In case of the use of B+ tree, an efficient node degree is also presented based on the experiment results. A new Timing Wheel index structure, which eliminates the insertion and deletion overhead of B+ tree, is proposed and analyzed.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.603-610
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• 1995

In this paper, we present a highly efficient simulation package which supports simulation from functional level to gate level. The package consists of a set of front-end tools, a logic simulator, named HSIM(Highly efficient logic SIMulator), and an waveform analyzer. The front-end tools include a netlist compiler, functional primitive compiler and behavioral compiler. Key feature of developed simulator is that the compiled behavioral models written in C language are directly executed in the simulation engine using incremental loader. By doing so, we achieved significant speed up as compared with the interpretive functional simulator. Experimental results show that HSIM runs about 55% faster than traditional unit-delay event-driven interpretive simulator.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1577-1580
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• 1987

This paper proposes a gate and functional level logic simulator which can be run on XENIX O.S. The simulator has hierarchical structure including Hardware Description Language compiler, Waveform Description Language compiler, and Simulation Command Language compiler. The Hardware Description Language compiler generates data structure composed of gate structure, wire structure, condition structure, and event structure. Simulation algorithm is composed of selective trace and event-driven methods. To improve simulation speed, Cross Referenced Linked List Structure ia defined in building the data structure of circuits.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.12
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• pp.439-446
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• 2016

In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction-based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.