• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.11 no.4
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• pp.55-68
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• 2007

First-order least-squares method of a distributed optimal control problem for the incompressible Navier-Stokes equations is considered. An optimality system for the optimal solution are reformulated to the equivalent first-order system by introducing velocity-flux variables and then the least-squares functional corresponding to the system is defined in terms of the sum of the squared $L^2$ norm of the residual equations of the system. The optimal error estimates for least-squares finite element approximations are obtained.

• Journal of the Korean Mathematical Society
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• v.46 no.5
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• pp.1007-1025
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• 2009

First-order least-squares method of a distributed optimal control problem for the incompressible Stokes equations is considered. An optimality system for the optimal solution are reformulated to the equivalent first-order system by introducing the vorticity and then the least-squares functional corresponding to the system is defined in terms of the sum of the squared $H^{-1}$ and $L^2$ norms of the residual equations of the system. Finite element approximations are studied and optimal error estimates are obtained. Resulting linear system of the optimality system is symmetric and positive definite. The V-cycle multigrid method is applied to the system to test computational efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.7
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• pp.610-614
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• 1991

This paper proposes a trajectory constrol fo a robot manipulator by using neural network. The inverse dynamic model of manipuator is learned by neural network. The manipulator is controlled by weight values of the learned neural network. The weight valuese is change with a torque of liner vontroller and a acceleration error. Phsically, the totlal torque for a manipualator is a sum of the liner controller torque and the nerural network controller torque. The proposed control effect is estimated by computer simulation.

• Korean Journal of Chemical Engineering
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• v.36 no.3
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• pp.356-367
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• 2019

This work presents an advanced and systematic approach to analytically design the optimal parameters of a two parameter second-order internal model control (IMC) filter that satisfies operational constraints on the output process, the manipulated variable as well as rate of change of the manipulated variable, for a first-order plus dead time (FOPDT) process. The IMC parameters are designed to minimize a control objective function composed of the weighted sum of the error between the process variable and the set point, and the rate of change of the manipulated variable, and to satisfy the desired constraints. The feasible region of the constrained IMC control parameters was graphically analyzed, as the process parameters and the constraints varied. The resulting constrained IMC control parameters were also used to find the corresponding industrial proportional-integral controller parameters of a Smith predictor structure.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.88-93
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• 2019

This paper is concerned with distributed fusion moving average prediction for continuous-time linear stochastic systems with multiple sensors. A distributed fusion with the weighted sum structure is applied to the optimal local moving average predictors. The distributed fusion prediction algorithm represents the optimal linear fusion by weighting matrices under the minimum mean square criterion. The derivation of equations for error cross-covariances between the local predictors is the key of this paper. Example demonstrates effectiveness of the distributed fusion moving average predictor.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.3
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• pp.195-205
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• 2020

This study addresses analysis on reactions which are induced in restraint system for airframe full-scale static structural test. This system restraints 6 degrees of freedom of a test article. It is valuable to study evaluating test error through analysis on the reactions which include all errors in a test. It is required to calculate fistly right reactions for the evaluation. This study focuses on calculation of the right reactions. The reaction is represented by sum of nominal reaction(Rn) and testing error reactions(Rce, Rerr) and is analyzed by two steps (inital vs relative reaction) in this study. It would evaluate intrinsic error at 0%DLL and error induced from applying test load, separately. Based on analysis using test data of a full-scale static test(canard type aircraft), resultant force of Rces and Rce_rs are distributed within 82.8N while resultant force of Rerr_rs shows to increase upto max. 808N as load level increment. Such well distribution of the Rce within the small range is caused from TMF values characteristics which are well distributed within -30N~40N. Additionally, it is shown through qualitative analysis on three components(X0, Y0, Z0) of the relative reaction(Rerr_r) that the reactions must be calculated with considering deformation of test article to calculate correctly reactions. This study shows also that equations characterizing deformation of components of test article are required to calculate the correct reactions, the equations must include information which will be used to calculate movement of all loading points.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.11
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• pp.2252-2260
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• 2015

In this paper, we propose a vehicular cooperative navigation system using GNSS, vision sensor and radar sensor that are frequently used in mass-produced cars. The proposed cooperative vehicular navigation system is a variant of the Hybrid-Sum Product Algorithm over Wireless Network (H-SPAWN), where we use vision and radar sensors instead of radio ranging(i.e.,UWB). The performance is compared and analyzed with respect to the sensors, especially the position estimation error decreased about fifty percent when using radar compared to vision and radio ranging. In conclusion, the proposed system with these popular sensors can improve position accuracy compared to conventional cooperative navigation system(i.e.,H-SPAWN) and decrease implementation costs.

• Journal of Korea Multimedia Society
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• v.11 no.3
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• pp.292-300
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• 2008

An algorithm for detecting a line segment in an image is presented using incremental pixel extension. We use a different approach from conventional algorithms, such as the Hough transform approach and the line segment grouping approach. The Canny edge is calculated and an arbitrary point is selected among the edge elements. After the arbitrary point is selected, a base line approximating the line segment is calculated and edge pixels within an arbitrary radius are selected. A weighted value is assigned to each edge pixel, which is selected by using the error of the distance and the direction between the pixel and the base line. A line segment is extracted by Jilting a line using the weighted least square method after determining whether selected pixels are linked or delinked using the sum comparison of the weights. The proposed algorithm is compared with two other methods and results show that our algorithm is faster and can detect the real line segment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.