• Journal of the Korea Institute of Military Science and Technology
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• v.3 no.1
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• pp.116-126
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• 2000

Turbo codes are the most exciting and potentially important development in coding theory in recent years. They were introduced in 1993 by Berrou, Glavieux and $Thitimajshima,({(1)}$ and claimed to achieve near Shannon-limit error correction performance with relatively simple component codes and large interleavers. A required Eb/N0 of 0.7㏈ was reported for BER of $10^{-5}$ and code rate of $l/2.^{(1)}$ However, to implement the turbo code system, there are various important details that are necessary to reproduce these results such as AGC gain control, optimal wordlength determination, and metric rescaling. Further, the memory required to implement MAP-based turbo decoder is relatively considerable. In this paper, we confirmed the accuracy of these claims by computer simulation considering these points, and presented a optimal wordlength for Turbo code design. First, based on the analysis and simulation of the turbo decoder, we determined an optimal wordlength of Turbo decoder. Second, we suggested the MAP decoding algorithm based on sliding-window method which reduces the system memory significantly. By computer simulation, we could demonstrate that the suggested fixed-point Turbo decoder operates well with negligible performance loss.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.25-34
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• 2012

This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.4 no.1
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• pp.62-77
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• 2010

Emerging applications with high data rates will need to transport bulk data reliably in wireless sensor networks. ARQ (Automatic Repeat request) or Forward Error Correction (FEC) code schemes can be used to provide reliable transmission in a sensor network. However, the naive ARQ approach drops the whole frame, even though there is a bit error in the frame and the FEC at the bit level scheme may require a highly complex method to adjust the amount of FEC redundancy. We propose a bulk data transmission scheme based on erasure-resilient code in this paper to overcome these inefficiencies. The sender fragments bulk data into many small blocks, encodes the blocks with LT codes and packages several such blocks into a frame. The receiver only drops the corrupted blocks (compared to the entire frame) and the original data can be reconstructed if sufficient error-free blocks are received. An incidental benefit is that the frame error rate (FER) becomes irrelevant to frame size (error recovery). A frame can therefore be sufficiently large to provide high utilization of the wireless channel bandwidth without sacrificing the effectiveness of error recovery. The scheme has been implemented as a new data link layer in TinyOS, and evaluated through experiments in a testbed of Zigbex motes. Results show single hop transmission throughput can be improved by at least 20% under typical wireless channel conditions. It also reduces the transmission time of a reasonable range of size files by more than 30%, compared to a frame ARQ scheme. The total number of bytes sent by all nodes in the multi-hop communication is reduced by more than 60% compared to the frame ARQ scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1864-1871
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• 2000

본 논문에서는 차세대 무선 통신 시스템에 적용이 가능한 새로운 FEC(Forward Error Correction) 부호화 방법으로 MLC(Multi-Level Convolutional) 부호화 방식을 제안한다. 차세대 무선통신서비스는 음성, 데이터, 영상 등 많은 종류의 서비스를 함으로써 데이터의 처리속도가 빠른 시스템이 요구된다. 데이터 처리시간을 단축시키기 위한 방법으로 다중 레벨을 이용하여 부호어를 만들어 내는 방식의 부호화 시스템을 설계하였다. MLC는 부호 처리시간을 단축시킬 뿐만 아니라 다양한 알고리즘을 이용해 부호어를 만들어 낼 수 있다는 특징을 가지게 된다. 모의실험은 MLC 코드의 두 가지 방법, Modulo- operation 방식과 Galois Field-Operation 방식을 이용하여 수행하였다. 또한 모의실험을 통하여 (s=2, T=2)인 경우가 MLC 부호기의 최적 연결다항식임을 알았다.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.69-72
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• 2005

As life style becomes to be complicated, lots of support technologies were developed. The bar code technology is one of them. It was renovating approach to goods industry. However, data storage ability in one dimension bar code came in limit because of industry growth. Two-dimension bar code was proposed to overcome one-dimension bar code. PDF417 bar code most commonly used in standard two-dimension bar codes is well defined at data decoding and error correction area. More works could be done in bar code image acquisition process. Applying various image enhancement algorithms, the recognition rate of PDF417 bar code is improved.

• Journal of Korea Multimedia Society
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• v.9 no.6
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• pp.728-734
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• 2006

Carrier interferometry code is considered as a promising scheme that provides significant performance improvement via frequency diversity effect. Space-time coding is commonly employed to achieve a performance gain through space diversity. The combination of these techniques and forward error correction coding will lead to enhanced system capacity and performance. This paper presents a low-density parity check (LDPC) coded space-time orthogonal frequency division multiplexing (OFDM) transmission scheme with carrier interferometry code for high-capacity and high-performance mobile multimedia communications. Computer simulations demonstrate that the proposed mobile multimedia transmission system offers a considerable performance improvement of approximately 9dB in terms of Eb/No in the Rayleigh fading channel with relatively low delay spread, in comparison with space-time OFDM. Performance gains are further increased, comparing with traditional OFDM systems.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2006.05a
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• pp.143-147
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• 2006

Wireless sensor networks(WSN) technology has various applications such as surveillance and information gathering in the uncontrollable area of human. One of major issues in WSN is the research for reducing the energy consumption and reliability of data. A system with forward error correction(FEC) can provide an objective reliability while using less transmission power than a system without FEC. In this paper, we propose to use LDPC codes of various code rate(0.53, 0.81, 0.91) for FEC for WSN. Also, we considered node-to-node interference in addition to AWGN channel. The proposed system has not only high reliable data transmission at low SNR, but also reduced transmission power usage.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.8
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• pp.765-772
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• 2006

The L2 Civil Signal (L2CS) will be transmitted by modernized IIR(IIR-M), IIF and all subsequent GPS satellites. It contains two codes of different length; CM code contains 10,230chips, repeats every 20milliseconds and is modulated with message data, and CL code contains 767,250chips, repeats every 1.5second Z-count and has no data modulation. And the message data is encoded for Forward Error Correction(FEC). The long code length is useful for weak signal, but it also requires very long acquisition time. Therefore, the structure of GPS Ll/L2C Correlator and the fast acquisition scheme are proposed in this paper.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.1166-1169
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• 2011

In this paper, we design a Circle dot Code, In our scheme, we design a dot patterns for increasing maximum capacity and also for increasing robustness to Affine Transformation. Our code Can be extended according number of data circle. We use three data circle vision code. In this type code, after acquiring camera images for the Circle dot Codes, and perform error correction decoding using four position symbols and six CRC symbols. We perform graph based dot code analysis which determines the topological distance between dot pixels. Our code can be bridged the real world and ubiquitous computing environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.