• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.11
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• pp.893-900
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• 2021

In this study, air density in a narrow test section is measured using a laser absorption spectroscopy system that detects oxygen absorption lines. An absorption line pair at 13156.28 and 13156.62 cm^-1 are detected. A gas chamber with a height of 40 mm is used as a narrow test section. A triangular spiral-shaped laser path is applied in the gas chamber to amplify absorption strength by extending laser beam path length. A well-known logarithm amplifier and a secondary amplifier are used to electrically amplify absorption signal. An AC-coupling is applied after the logarithm amplifier for signal saturation prevention and noise suppression. Procedure of calculating spectral absorbance from output signal is introduced considering the logarithm amplifier circuit configuration. Air density is determined by fitting the theoretically calculated spectral absorbance to the measured spectral absorbance. Test conditions with room temperature and a pressure range of 10~100 kPa are made in a gas chamber using a Bourdon pressure gauge. It is confirmed that air density in a narrow test section can be measured within a 16 % error through absorption signal amplification using a triangular spiral-shaped beam path and a logarithm amplifier.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.242-246
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• 2001

The alternated forward multi resonant converter (AT forward MRC) is studied on the transient response and the measured loop gain for stability. The compensator is composed of the error amplifier with 3 poles and 2 zeros. This is optimized through the experiment with HP4194A network analyzer. We are initiated by the thinking of how to make the stabilization from the experimental results of loop gain curves. The loop gain, low frequency gain and gain margin are more improved through the experimental considerations. Also, the transient response is more enhanced effectively.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.53-59
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• 1994

A new fully differential sample-and-hold circuit which can effectively compensate the offset voltage of an operational amplifier and the charge injection of a MOS switch is presented. The proposed circuit shows a true sample-and-hold function without a reset period or an input-track period. The prototype fabricated using a 1.2$\mu$m double-polysilicon CMOS process occupies an area of 550$\mu$m$\times$288$\mu$m and the error of the sampled ouput is 0.056% on average for 3V input at DC.

• ETRI Journal
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• v.28 no.4
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• pp.513-516
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• 2006

Experimental demonstration of bipolar spectral encoding code-division multiple-access with modified pseudorandom noise codes is presented. Bipolar spectral encoding is achieved with an erbium-doped fiber amplifier amplified spontaneous emission source and arrayed waveguide gratings. The bit-error rate performance of 1.25 Gbps signal transmission over 80 km single mode fiber is measured in a multiple-user environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.1-1
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• 2001

DRAM에서 셀 캐패시터의 누설 전류 영향을 고려하여 소프트 에러율을 예측하였다. DRAM의 동작 과정에서 누설 전류의 영향으로 셀 캐패시터는 전하량이 감소하고, 이에 따른 소프트 에러율을 DRAM의 각 동작 모드에 대하여 계산하였다. 누설 전류가 작을 경우에는 /bit mode가 소프트 에러에 취약했지만, 누설전류가 커질수록 memory 모드가 소프트 에러에 가장 취약함을 보였다. 실제 256M급 DRAM의 구조에 적용하여, 셀 캐패시턴스, bit line 캐패시턴스, sense amplifier의 입력 전압 감도들이 변화할 때 소프트 에러에 미치는 영향을 예측하였고, 이 결과들은 차세대 DARM 연구의 최적 셀 설계에 이용될 수 있다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.137-141
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• 2000

본 논문에서는 전력증폭기의 선형성을 광대역으로 개선하기 위하여 Delay 라인의 영향에 대하여 고려하려다. 사용된 전력 증폭기의 이득은 37dB이고, 3단의 l1W급으로 설계되었다. Error 증폭기는 4단으로 설계되었으며 이득은 55dB이다. 그리고 크기와 위상을조절하기 위한 장치로 Vector modulator를 사용하였으며, 또한 방향성 결합기 및 전력분배기를 설계하였다. 각 모듈을 통합하여 주파수 2.11GHz에서 2.2GHz까지 Delay 특성을 고려한 광대역 선형 전력 증폭기를 설계하였으며 대역폭이 30MHz에 걸쳐 IMD성분의 제거 특성이 25dB이상의 개선 효과를 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.8
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• pp.849-853
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• 2014

In micro-scale electromechanical systems, the power to perform accurate position sensing often greatly exceeds the power needed to generate motion. This paper explores the implications of sampling rate and amplifier noise density selection on the performance of a system identification algorithm using a capacitive sensing circuit. Specific performance objectives are to minimize or limit convergence rate and power consumption to identify the dynamics of a rotary micro-stage. A rearrangement of the conventional recursive least-squares identification algorithm is performed to make operating cost an explicit function of sensor design parameters. It is observed that there is a strong dependence of convergence rate and error on the sampling rate, while energy dependence is driven by error that may be tolerated in the final identified parameters.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1260-1264
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• 1990

A voltage controlled CMOS operational transconductance amplifier (OTA), whose transconductance is directly proportional to the DC bias voltage, has been designed for many electronic circuit applications. It consists of a differential pair and three ourrent mirrors. The SPICE simulation shows that the conversion sensitivity of the OTA is 41.817 \ulcornerho/V and the linearity error is less than 0.402% over a bias voltage range from -2. OV to 1. OV. Electrically tunalble filters based on voltage controlled impedances, which are realized with OTA's, also have been designed. The SPICE simulation shows that a second-order bandpass filter, whose center frequency is 23KHz at -1. OV, has the conversion sensitivity 6.6KHz/V and the linearity error less than 0.822% over a voltage range from -2.OV tp 1.OV, Tne OTA has been laid out with the 3\ulcorner n-well CMOS design rule adopted in ISRC (inter-university semiconductor research center). The chip size was about $0.756x0.945mm^2$.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.457-461
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• 1988

In this study an one-board micom controlled precision temperature control system has been developed. The digital temperature control system is consisted of an one-board micom as digital controller, a 12-bit A/D and D/A converter, a power amplifier, a NTC thermister, a preamplfier and a heat chamber. An operating control program for the control system was written in Z80 machine language. A Dual-PID predictor control algorithm was proposed. Experments were conducted with different sampling time and limitted error value. As a result, the temperature in a heat chamber can be well controlled within +- 0.2 .deg.C when the sampling time was applied to 10 sec and the limitted error value +- 0.5 .deg.C under the dual-PID predictor control algorithm. By means of one-board micom overall system has been reduced in size and volume, thus the system becomes compact and less expensive.