• Title/Summary/Keyword: Error Detection Code

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Voice Activity Detection Algorithm base on Radial Basis Function Networks with Dual Threshold (Radial Basis Function Networks를 이용한 이중 임계값 방식의 음성구간 검출기)

  • Kim Hong lk;Park Sung Kwon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.12C
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    • pp.1660-1668
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    • 2004
  • This paper proposes a Voice Activity Detection (VAD) algorithm based on Radial Basis Function (RBF) network using dual threshold. The k-means clustering and Least Mean Square (LMS) algorithm are used to upade the RBF network to the underlying speech condition. The inputs for RBF are the three parameters in a Code Exited Linear Prediction (CELP) coder, which works stably under various background noise levels. Dual hangover threshold applies in BRF-VAD for reducing error, because threshold value has trade off effect in VAD decision. The experimental result show that the proposed VAD algorithm achieves better performance than G.729 Annex B at any noise level.

Optimization of a Systolic Array BCH encoder with Tree-Type Structure

  • Lim, Duk-Gyu;Shakya, Sharad;Lee, Je-Hoon
    • International Journal of Contents
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    • v.9 no.1
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    • pp.33-37
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    • 2013
  • BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

Performance of the Long Code MMSE Detector With Pilot Channel in the Presence of Rayleigh Fading

  • Lee, Yun-Soo;Chinn, Yong-Oak
    • Journal of information and communication convergence engineering
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    • v.5 no.4
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    • pp.333-338
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    • 2007
  • In this paper we propose a new structure of the long code MMSE receiver with pilot channel, which maintians excellent symbol detection capability even in the presence of Rayleigh fading. We explain analytically how the stability of the receiver weight vector, which is critical to the system performance, can be achieved by compensating the error signal as well as received signal vector distorted by fading channel. Computer simulation shows while maintaining better performance than the conventional matched filter receiver, the proposed long code MMSE receiver can extend its period up to $16{\times}T_b$ in a fading environment.

Design of Kinematic Position-Domain DGNSS Filters (차분 위성 항법을 위한 위치영역 필터의 설계)

  • Lee, Hyung Keun;Jee, Gyu-In;Rizos, Chris
    • Journal of Advanced Navigation Technology
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    • v.8 no.1
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    • pp.26-37
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    • 2004
  • Consistent and realistic error covariance information is important for position estimation, error analysis, fault detection, and integer ambiguity resolution for differential GNSS. In designing a position domain carrier-smoothed-code filter where incremental carrier phases are used for time-propagation, formulation of consistent error covariance information is not easy due to being bounded and temporal correlation of propagation noises. To provide consistent and correct error covariance information, this paper proposes two recursive filter algorithms based on carrier-smoothed-code techniques: (a) the stepwise optimal position projection filter and (b) the stepwise unbiased position projection filter. A Monte-Carlo simulation result shows that the proposed filter algorithms actually generate consistent error covariance information and the neglection of carrier phase noise induces optimistic error covariance information. It is also shown that the stepwise unbiased position projection filter is attractive since its performance is good and its computational burden is moderate.

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A study for chirp signal method & system implementation in the PLC modem with low speed (저속 PLC 모뎀에서의 Chirp 신호 방식과 시스템 구현에 관한 연구)

  • Jeong, Young-Hwa;Sang-Gun Lee
    • The Journal of Information Technology
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    • v.7 no.3
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    • pp.37-45
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    • 2004
  • The representative communication method which is applied in the low-speed power line communication modem with 60bps is single carrier method. It has been used mainly for the control. The single carrier method is very sensitive to a power line communication channel environment. Specially, the severe attenuation of the transmission signal according to the notch characteristics of channel becomes the main cause of communication error. Domestic power line channel environment has this notable feature. In this paper, we implemented the low-speed power line communication system which used the chirp signal method to be strong in notch and noise characteristics. In this research, we proposed the method which transmits 1- '1 Unit symbol Chirp signal' with a 100${\mu}s$ time within 1ms for 1 bit. Also it applied for the Convolution code for an error correction and the Manchester code for a collision perception and an error detection. It used the method which uses the bit correlator for signal detection in the receiver parts. We confirmed that the communication method of the chirp method has a excellent performance compared to single carrier methods with a result of experiment of the low-speed power line communication system with the 60bps.

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A Study on performance improvement of MMSE Multi-User Detector (MMSE 다중사용자 검출기의 성능 향상에 관한 연구)

  • Yoo, Dong-Kwan
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.1 s.45
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    • pp.145-154
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    • 2007
  • In this paper, an improved detection method is proposed by supplementing various types of Multi-Path gam for a MMSE Multi-User detecter. This method is proposed to complement the shortcomings of the conventional detection method which is used for multiuser detection in STBC(Space-Time Block Code) CDMA system. We analyzed the improved method in bit error probability viewpoint and compared the result with that of the conventional method. In this result, we showed that the improved method obtains better performance of bit error probability than the conventional method when parameters such as delay, number of user and SNR are changed.

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LDPC Coding for image data and FPGA Implementation of LDPC Decoder (영상 정보의 LDPC 부호화 및 복호기의 FPGA구현)

  • Kim, Jin Su;Jaegal, Dong;Byon, Kun Sik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.05a
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    • pp.887-890
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    • 2009
  • To transmit information over a channel in the presence of noise, there needs some technique to code the information. One of the coding techniques used for error detection and correction close to the Shannon limit is Low Density Parity Code. LDPC and decoding characteristic features by sum-product algorithm are matched for the performance to Turbo Code, RA(Repeat Accumulate) code, in case of very long code length of LDPC surpass their performance. This paper explains LDPC coding scheme of image data and decoding scheme, implements LDPC decoder in FPGA.

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Detection of Potential Memory Access Errors based on Assembly Codes (어셈블리어 코드 기반의 메모리 오류 가능성 검출)

  • Kim, Hyun-Soo;Kim, Byeong-Man;Bae, Hyun-Seop;Chung, In-Sang
    • The KIPS Transactions:PartD
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    • v.18D no.1
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    • pp.35-44
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    • 2011
  • Memory errors can cause not only program malfunctions but also even unexpected system halt. Though a programmer checks memory errors, some memory errors with low occurrence frequency are missed to detect. In this paper, we propose a method for effectively detecting such memory errors using instruction transition diagrams through analyzing assembly codes obtained by disassembling an executable file. Out of various memory errors, local memory return errors, null pointer access errors and uninitialized pointer access errors are targeted for detection. When applying the proposed method to various programs including well-known open source programs such as Apache web server and PHP script interpreter, some potential memory errors are detected.

Self-Encoded Spread Spectrum with Iterative Detection under Pulsed-Noise Jamming

  • Duraisamy, Poomathi;Nguyen, Lim
    • Journal of Communications and Networks
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    • v.15 no.3
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    • pp.276-282
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    • 2013
  • Self-encoded spread spectrum (SESS) is a novel modulation technique that acquires its spreading code from a random information source, rather than using the traditional pseudo-random noise (PN) codes. In this paper, we present our study of the SESS system performance under pulsed-noise jamming and show that iterative detection can significantly improve the bit error rate (BER) performance. The jamming performance of the SESS with correlation detection is verified to be similar to that of the conventional direct sequence spread spectrum (DSSS) system. On the other hand, the time diversity detection of the SESS can completely mitigate the effect of jamming by exploiting the inherent temporal diversity of the SESS system. Furthermore, iterative detection with multiple iterations can not only eliminate the jamming completely but also achieve a gain of approximately 1 dB at $10^{-3}$ BER as compared with the binary phase shift keying (BPSK) system under additive white gaussian noise (AWGN) by effectively combining the correlation and time diversity detections.

Soft Error Detection for VLIW Architectures with a Variable Length Execution Set (Variable Length Execution Set을 지원하는 VLIW 아키텍처를 위한 소프트 에러 검출 기법)

  • Lee, Jongwon;Cho, Doosan;Paek, Yunheung
    • KIPS Transactions on Computer and Communication Systems
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    • v.2 no.3
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    • pp.111-116
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    • 2013
  • With technology scaling, soft error rate has greatly increased in embedded systems. Due to high performance and low power consumption, VLIW (Very Long Instruction Word) architectures have been widely used in embedded systems and thus many researches have been studied to improve the reliability of a system by duplicating instructions in VLIW architectures. However, existing studies have ignored the feature, called VLES (Variable Length Execution Set), which is adopted in most modern VLIW architectures to reduce code size. In this paper, we propose how to support instruction duplication in VLIW architecture with VLES. Our experimental results demonstrate that a VLIW architecture with VLES shows 64% code size decrement on average at the cost of about 4% additional cell area as compared to the case of a VLIW architecture without VLES when instruction duplication is applied to both architectures. Also, it is shown that the case with VLES does not cause extra execution time compared to the case without VLES.