• International Journal of Knowledge Content Development & Technology
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• 제5권2호
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• pp.75-101
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• 2015

In this paper, we investigate the notion of error correction memory applied to technical texts. The main purpose is to introduce flexibility and context sensitivity in the detection and the correction of errors related to Constrained Natural Language (CNL) principles. This is realized by enhancing error detection paired with relatively generic correction patterns and contextual correction recommendations. Patterns are induced from previous corrections made by technical writers for a given type of text. The impact of such an error correction memory is also investigated from the point of view of the technical writer's cognitive activity. The notion of error correction memory is developed within the framework of the LELIE project an experiment is carried out on the case of fuzzy lexical items and negation, which are both major problems in technical writing. Language processing and knowledge representation aspects are developed together with evaluation directions.

• 한국소프트웨어감정평가학회 논문지
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• 제16권2호
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• pp.69-76
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• 2020

본 논문에서는 오류 수정 난이도를 나타내는 지표인 오류 수정 시간을 사용하여 소프트웨어 최적 출시 시점 결정 문제를 연구하였다. 특히 기존의 오류 수정 시간을 고려한 소프트웨어 신뢰도 성장 모델에서 오류 발견 시간과 수정 시간이 독립적이라는 가정을 수정하고, 오류 발견 시간과 수정 시간의 상관관계를 표현할 수 있는 일반적인 프레임워크 모델을 설정하여 소프트웨어 최적 출시 시점을 결정해 보고자 하였다. 그 결과 테스트 초기에 수정 시간이 걸리는 오류를 발견하는 것이 경제적인 관점에서 중요하다는 것을 알 수 있었다. 최적의 소프트웨어 출시 시점을 결정하는 데에 있어서 오류발견시간과 오류수정시간의 상관관계를 분석하는 것이 매우 중요하다는 결론을 얻을 수 있었다.

• 한국정보통신학회논문지
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• 제26권11호
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• 제어로봇시스템학회논문지
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• 제17권11호
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• pp.1101-1105
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• 2011

Radiation particles can introduce temporary errors in memory systems. To protect against these errors, so-called soft errors, error detection and correcting codes are used. In addition, scrubbing is applied which is a fundamental technique to avoid the accumulation of soft errors. This paper introduces an optimal scrubbing scheme, which is suitable for a system with auto error detection and correction logic. An auto error detection and correction logic can correct soft errors without CPU's writing operation. The proposed scrubbing scheme leads to maximum reliability by considering both allowable scrubbing load and the periodic accesses to memory by the tasks running in the system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.106-109
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• 2002

In the integrated systems, that is integrated digital TV(DTV) internet and home automation, like home server, is needed integration of digital TV video signal and computer graphic signal. The graphic signal is operating at the high speed and has time-divide-stream. So the re-request of data is not easy at the time of error detection. therefore EDAC algorithm is efficient. This paper presents the efficiency error detection auto correction(EDAC) for conversion of graphics signal to DTV video signal. A presented EDAC algorithms use the modified Hamming code for enhancing video quality and reliability. A EDAC algorithm of this paper can detect single error, double error, triple error and more error for preventing from incorrect correction. And it is not necessary an additional memory. In this paper The comparison between digital TV video signal and graphic signal, a EBAC algorithm and a design of conversion graphic signal to DTV signal with EDAC function is described.

• 한국전자통신학회논문지
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• 제13권4호
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• pp.721-728
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• 2018

본 논문은 다양한 구조의 선형 블록 오류정정코드를 소개하고, 이를 회로로 구현하여 비교 분석한 결과를 보여주고 있다. 메모리 시스템에서는 잡음 전력으로 인한 비트 오류를 방지하기 위해 ECC(: Error Correction Code)가 사용되어 왔다. ECC의 종류에는 SEC-DED(: Single Error Correction Double Error Detection)와 SEC-DED-DAEC(: Double Adjacent Error Correction)가 있다. SEC-DED인 Hsiao 코드와 SEC-DED-DAEC인 Dutta, Pedro 코드를 각각 Verilog HDL을 이용해 설계 후 $0.35{\mu}m$ CMOS 공정을 사용해 회로로 합성하였다. 시뮬레이션에 의하면 SEC-DED회로는 인접한 두 개의 비트 오류를 정정하지 못하지만 적은 회로 사용면적과 빠른 지연 시간의 장점이 있으며, SEC-DED-DAEC 회로의 경우 Pedro 코드와 Dutta 코드 간에는 면적, 지연 시간의 차이가 없으므로 오류 정정률이 개선된 Pedro 코드를 사용하는 것이 더 효율적임을 알 수 있다.

• 전기학회논문지
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• 제59권2호
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• 정보처리학회논문지:소프트웨어 및 데이터공학
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• 제4권1호
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• pp.45-56
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• 2015

본 연구에서는 문맥 정보를 함께 고려해야만 인식할 수 있는 단어 오류에 대하여 오류 인식 방법과 수정 후보 생성 방법을 제안한다. 이 문제는 기존의 영어권에서 이미 많이 다룬 연구 주제이다. 본 연구에서는 영어 자동채점 시스템에서 사용하도록 특화된 방법을 제안한다. 문맥 정보를 고려한 단어 오류 검사에서는 자주 혼동되어 사용되는 단어집합(confusion set)을 활용한다. 비영어권 사용자의 작문 특성을 반영하기 위해 기존의 영어권에서 구축한 혼동집합 이외에 자동으로 혼동집합을 구축하여 실험해 보았다. 또한 품사 중의성으로 인해 기존의 구문오류 검사기가 다루지 못하는 오류를 정의하고 오류 인식과 오류수정 후보를 생성하는 방법을 제안한다. 실제 한국어가 모국어이면서 초/중급 작문 수준의 수험생들이 작성한 영어 문장에 대해 평가해 본 결과, 약 70.48%의 f1 값을 얻어 기존의 영어권 결과에 비해 뒤지지 않는 성능을 보였다.

• 대한전자공학회논문지
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• 제25권2호
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• pp.204-210
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• 1988

The residue number system offers the possibility of high-speed operation and error detection/correction because of the separability of arithmetic operations on each digit. A compact residue arithmetic module named the self-checking pulse-train residue arithmetic circuit is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detection is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. In this case, the error correcting circuit is imposed in series to non-redundant system. This design method has an advantage of compact hardware. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter is practically implemented, and its fault-tolerant ability is proved by noise injection testing.