• Title/Summary/Keyword: Error Correcting Codes

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The Analysis about Channel Code Performance of Underwater Channel (수중통신채널에서 고려되는 채널 부호의 성능 분석)

  • Bae, Jong-Tae;Kim, Min-Hyuk;Choi, Suk-Soon;Jung, Ji-Won;Chun, Seung-Yong;Dho, Kyeong-Cheol
    • The Journal of the Acoustical Society of Korea
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    • v.27 no.6
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    • pp.286-295
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    • 2008
  • Underwater acoustic communication has multi path error because of reflection by sea-level and sea-bottom. The multipath of underwater channel causes signal distortion and error floor. In this paper, we consider the use of various channel coding schemes such as RS code, convolutional code, cross-layer code and LDPC code in order to compensate the multipath effect in underwater channel. As shown in simulation results, characteristic of multipath error is similar to that of random error, so interleaver has little effect for error correcting. For correcting of error floor by multipath error, it is necessary strong channel codes like LDPC code that is similar to Shannon's limit. And the performance of concatenated codes including RS codes has better performance than using singular channel codes.

A NEW UPPER BOUND FOR SINGLE ERROR-CORRECTING CODES

  • Kim, Jun-Kyo
    • Bulletin of the Korean Mathematical Society
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    • v.38 no.4
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    • pp.797-801
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    • 2001
  • The purpose of this paper is to give an upper bound for A[n,4], the maximum number of codewords in a binary code of word length n with minimum distance 4 between codewords. We have improved upper bound for A[12k+11,4]. In this correspondence we prove $A[23,4]\leq173716$.

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Improved Decoding Algorithm on Reed-Solomon Codes using Division Method (제산방법에 의한 Reed-Solomon 부호의 개선된 복호알고리듬)

  • 정제홍;박진수
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.11
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    • pp.21-28
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    • 1993
  • Decoding algorithm of noncyclic Reed-Solomon codes consists of four steps which are to compute syndromes, to find error-location polynomial, to decide error-location, and to solve error-values. There is a decoding method by which the computation of both error-location polynomial and error-evaluator polynimial can be avoided in conventional decoding methods using Euclid algorithm. The disadvantage of this method is that the same amount of computation is needed that is equivalent to solve the avoided polynomial. This paper considers the division method on polynomial on GF(2$^{m}$) systematically. And proposes a novel method to find error correcting polynomial by simple mathematical expression without the same amount of computation to find the two avoided polynomial. Especially. proposes the method which the amount of computation to find F (x) from the division M(x) by x, (x-1),....(x--${\alpha}^{n-2}$) respectively can be avoided. By applying the simple expression to decoding procedure on RS codes, propses a new decoding algorithm, and to show the validity of presented method, computer simulation is performed.

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Enhancing Robustness of Information Hiding Through Low-Density Parity-Check Codes

  • Yi, Yu;Lee, Moon-Ho;Kim, Ji-Hyun;Hwang, Gi-Yean
    • Journal of Broadcast Engineering
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    • v.8 no.4
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    • pp.437-451
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    • 2003
  • With the rapid growth of internet technologies and wide availability of multimedia computing facilities, the enforcement of multimedia copyright protection becomes an important issue. Digital watermarking is viewed as an effective way to deter content users from illegal distributions. In recent years, digital watermarking has been intensively studied to achieve this goal. However, when the watermarked media is transmitted over the channels modeled as the additive white Gaussian noise (AWGN) channel, the watermark information is often interfered by the channel noise and produces a large number of errors. So many error-correcting codes have been applied in the digital watermarking system to protect the embedded message from the disturbance of the noise, such as BCH codes, Reef-Solomon (RS) codes and Turbo codes. Recently, low-density parity-check (LDPC) codes were demonstrated as good error correcting codes achieving near Shannon limit performance and outperforming turbo codes nth low decoding complexity. In this paper, in order to mitigate the channel conditions and improve the quality of watermark, we proposed the application of LDPC codes on implementing a fairly robust digital image watermarking system. The implemented watermarking system operates in the spectrum domain where a subset of the discrete wavelet transform (DWT) coefficients is modified by the watermark without using original image during watermark extraction. The quality of watermark is evaluated by taking Into account the trade-off between the chip-rate and the rate of LDPC codes. Many simulation results are presented in this paper, these results indicate that the quality of the watermark is improved greatly and the proposed system based on LDPC codes is very robust to attacks.

Design of an Encoder and Decoder Using Reed-Muller Code (Reed-Muller 부호의 인코더 및 디코더 설계)

  • 김영곤;강창언
    • Proceedings of the Korean Institute of Communication Sciences Conference
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    • 1984.10a
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    • pp.15-18
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    • 1984
  • The majority - logic decoding algorithm for Geometry code is more simply imlemented than the known decoding algorithm for BCH codes. Thus, the moderate code word, Geometry codes provide rather effective error control. The purpose of this paper is to investigate the Reed - Muller code and to design the encoder and decoder circuit and to find the performance for (15, 11) Reed - muller code. Experimental results show that the system has not only single error - correcting ability but also good performance.

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Recent Successive Cancellation Decoding Methods for Polar Codes

  • Choi, Soyeon;Lee, Youngjoo;Yoo, Hoyoung
    • Journal of Semiconductor Engineering
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    • v.1 no.2
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    • pp.74-80
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    • 2020
  • Due to its superior error correcting performance with affordable hardware complexity, the Polar code becomes one of the most important error correction codes (ECCs) and now intensively examined to check its applicability in various fields. However, Successive Cancellation (SC) decoding that brings the advanced Successive Cancellation List (SCL) decoding suffers from the long latency due to the nature of serial processing limiting the practical implementation. To mitigate this problem, many decoding architectures, mainly divided into pruning and parallel decoding, are presented in previous manuscripts. In this paper, we compare the recent SC decoding architectures and analyze them using a tree structure.

Quasi-Cyclic LDPC Codes using Superposition Matrices and Their Layered Decoders for Wibro Systems (Wibro 시스템에서 중첩 행렬을 이용한 준 순환 LDPC 부호의 설계 및 계층 복호기)

  • Shin, Beom-Kyu;Park, Ho-Sung;Kim, Sang-Hyo;No, Jong-Seon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.2B
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    • pp.325-333
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    • 2010
  • Most communication systems including Wibro use quasi-cyclic LDPC codes composed of circulants. However, it is very difficult to design quasi-cyclic(QC) LDPC codes with optimal degree distribution satisfying conditions on layered decoding and girth due to the restriction of the size of its base matrix. In this paper, we propose a good solution by introducing superposition matrices to QC LDPC codes. We derive the conditions on checking girth of QC LDPC codes with superposition matrices, and propose new decoder to support layered decoding both for original QC LDPC codes and their modifications with superposition matrices. Simulation results show considerable improvements to convergence speed and error-correcting performance of proposed scheme which adopts QC LDPC codes with superposition matrices.

AN UPPER BOUND ON THE NUMBER OF PARITY CHECKS FOR BURST ERROR DETECTION AND CORRECTION IN EUCLIDEAN CODES

  • Jain, Sapna;Lee, Ki-Suk
    • Journal of the Korean Mathematical Society
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    • v.46 no.5
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    • pp.967-977
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    • 2009
  • There are three standard weight functions on a linear code viz. Hamming weight, Lee weight, and Euclidean weight. Euclidean weight function is useful in connection with the lattice constructions [2] where the minimum norm of vectors in the lattice is related to the minimum Euclidean weight of the code. In this paper, we obtain an upper bound over the number of parity check digits for Euclidean weight codes detecting and correcting burst errors.

A Versatile Reed-Solomon Decoder for Continuous Decoding of Variable Block-Length Codewords (가변 블록 길이 부호어의 연속 복호를 위한 가변형 Reed-Solomon 복호기)

  • 송문규;공민한
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.3
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    • pp.187-187
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    • 2004
  • In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.