• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1303-1312
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• 2008

Satellite WiBro system has high PAPR characteristics in addition to the nonlinear characteristics of the power amplifier. These characteristics reduce amplifying efficiency of the power amplifier and also cause high error rate and interference with adjacent channels. This paper proposed satellite WiBro based system to reduce input signal's IBO of TWTA remarkably by adapting simultaneously PAPR reduction techniques, active-constellation extension technique and pre-distortion technique.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• Journal of IKEEE
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• v.12 no.3
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• pp.176-183
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• 2008

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit as a block. The Saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device, achieved the high efficiency near 95% at 100mA output current. And DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Journal of electromagnetic engineering and science
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• v.12 no.4
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• pp.290-292
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• 2012

This paper proposes a setup for a best multisine design method that uses a time-domain optimization. The method is based on minimization of the time-domain error, so its resulting multisine has a very accurate ACLR estimation. This is because its probability distribution and sample-to-sample correlation are close to those of the original signal, which are crucial for the testing of nonlinear power amplifiers. In addition, a hyperbolic-tangent function is introduced to control the ripple of tone magnitudes within signal bandwidth. For the verification, multisines were generated and compared for many aspects such as normalized error, in-band ripple, and ACLR estimation. Test results with different numbers of tones provide supporting evidence that the suggested multisine design has better ripple suppression, by up to 7 dB, and better accuracy, by up to 0.2 dB, when compared to the conventional method. The accuracy of the ACLR was improved by about 5 dB when the number of tones was 4. The suggested method improves the ACLR estimation performance of multisine testing due to its closer resemblance to the target modulation signal.

• Korean Journal of Optics and Photonics
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• v.23 no.6
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• pp.264-268
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• 2012

In this paper, we propose a new method for broadcasting in a WDM-PON system which has the merits of a simple and cost effective structure. It can be constructed using only an ASE (Amplified Spontaneous Emission) light source and a PI-RSOA (Polarization Independent - Reflective Semiconductor Optical Amplifier). Error-free broadcast signal transmission over 30 Km for 24 channels at 1.25 Gb/s has been successfully demonstrated.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.25-30
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• 2010

This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

• Journal of Astronomy and Space Sciences
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• v.27 no.3
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• pp.221-230
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• 2010

A 4+12+16 amplitude phase shift keying (APSK) modulation outperforms other 32-APSK modulations in a nonlinear additive white Gaussian noise (AWGN) channel because of its intrinsic robustness against AM/AM and AM/PM distortions caused by the nonlinear characteristics of a high-power amplifier. Thus, this modulation scheme has been adopted in the digital video broadcasting-satellite2 European standard. And it has been considered for high rate transmission of telemetry data on deep space communications in consultative committee for space data systems which provides a forum for discussion of common problems in the development and operation of space data systems. In this paper, we present an improved bits-to-symbol mapping scheme with a better bit error rate for a 4+12+16 APSK signal in a nonlinear AWGN channel and propose a simple signal detection algorithm for the 4+12+16 APSK from the presented bit mapping.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1115-1125
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• 1994

In this paper, an efficient concatenated coding scheme under the satellite channel is presented. The performance of this scheme in terms of bit error rate versus energy per information bit over white gaussian noise power density E/N has been evaluated via computer simulation as a function of various system parameters. To achieve accuracy in simulation results, the distortions caused from the satellite channel, such as the nonlinearity of the TWTA(traveling wave tube amplifier), signal distortions of the input and output filters, has been considered. The simulation results show that, through using the 2/3 punctured convolutional code as the inner code of the concatenated code system, the coding rate can be improved more over 16%, while maintaining the same system complexity and bit error performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.79-82
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• 2017

In this paper, we proposed the wireless communication system using millimeter-wave envelope detector. The sub-harmonic mixer based on schottky barrier diode was used in the transmitter. The receiver was used millimeter-wave envelope detector. The transmitter was composed of schottky diode sub-harmonic mixer, frequency tripler, and horn antenna. The receiver was composed of horn antenna, millimeter-wave envelope detector, low pass filter, base band amplifier, and limiting amplifier. At 1.485 Gbps and 300 GHz, the eye-diagram showed a very good performance as measured by the error free. Communication distance is reduced compared to the heterodyne receiver, but compact and lightweight is possible.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1641-1644
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• 2005

현재의 인터넷과 같은 전자 통신망과 멀티미디어 시스템의 발달은 고속의 대용량 데이터 전송을 필요로 한다. 초고속 통신 시스템에서의 고속 데이터 전송은 주로 광섬유를 사용하는 광통신으로 이루어지고 있다. FTTH(Fiber To The Home)와 같은 광통신 시스템은 멀티미디어 커뮤니케이션을 위해 필요한 큰 데이터 전송률을 제공할 수 있기 때문에 더욱 더 중요성이 높아지고 있으며 이러한 광통신 시스템에서는 통신환경의 영향을 적게 받고 외부 조절이나 부품이 필요하지 않는 수신기 IC 의 개발이 요구되고 있다. 일반적으로 광통신 수신기에는 고속 동작에 적합한 특성을 가진 GaAs-MESFET 가 사용되고 있으나, 본 논문에서는 0.35um CMOS 2-poly 4-metal 공정을 이용하여 5Gbps 광수신기를 설계하였다. 설계된 수신기는 Preamplifier, Main amplifier, ABC 회로로 구성되어 있다. Transimpedance amplifier 형태의 Preamplifier 는 광검출기에 의해 생성된 전류 신호를 전압 신호로 변환한다. ABC 회로는 Peak_Hold 회로와 Bottom_Hold 회로로 구성되어 있다. 기존의 Peak_Hold 회로에서는 다이오드와 hold capacitor 를 이용하여 peak 값을 검출하도록 되어 있는데, 다이오드를 이용하는 경우 작은 입력 신호전압의 Peak 값을 검출하는 데 한계가 있다. 이러한 단점을 보완하고자 전류 거울형태의 Peak_Hold 회로를 설계하였다. 전류거울(current mirror)형태의 출력 신호의 duty error 를 줄이고 비트 에러율(Bit Error Rate)을 개선하는데 효과적이었다. 설계된 광수신기는 30dB 의 입력 dynamic range 와 입력 capacitance 3pF 에서 80MHz 의 대역폭을 가진다. 전력 소비량은 3.3V 전원 전압이 인가된 경우 약 150mW 정도이다.