• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.932-934
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• 2006

A relationship between discharge delay time and the aging method were investigated: A-Y (Address electrode - Scan electrode) aging and conventional X-Y(Common electrode - Scan electrode) aging with the variation of sustain voltage beyond self-erasing discharge. Although A-Y aging decreases discharge delay time, it has several drawbacks like non-uniformity of discharge, degradation of luminous efficiency and a color temperature. In a conventional aging condition which is carried out near the mid-margin voltage, discharge delay time is short in low voltage and high frequency condition. As an alternative to conventional voltage aging, high voltage aging is suggested which is carried out at self-erasing sustain voltage region. High voltage aging shows lower discharge delay time and fast aging speed than conventional voltage aging.

• Journal of Information Display
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• 제7권1호
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• pp.30-34
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• 2006

A sub-field rearrangement driving method has been proposed to reduce a DFC (Dynamic False Contour) phenomenon in plasma display panels. The proposed driving method expresses 256 gray levels with 16 sub-fields, while conventional one uses only 8 sub-fields. Notwithstanding the increase in the number of sub-fields, the display time is similar to the conventional 8 sub-fields driving method by appropriate choosing selective writing and selective erasing for sub-fields.

• 전기학회논문지
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• 제62권1호
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• pp.83-89
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• 2013

In order to reduce the power consumption in international standard IEC62087, the luminance efficiency should be improved at the low discharge load rather than at the high discharge load. Thus, this paper analysed the characteristics of the discharge at the panels with ITO Gap of $65{\mu}m$, $80{\mu}m$, and $100{\mu}m$ in 50-inch PDP with FHD resolution. It was well known that the long gap panel improves the luminance and the luminous efficiency. However, it is very difficult to drive the panel due to high driving voltage. When the normal driving method was applied at the panel with ITO gap of $100{\mu}m$, the phenomenon of the double peak was generated in the sustain period. We confirmed that main factor of the double peak is the self-erasing discharge. When the CLHS driving method was applied at the panel with ITO gap of $100{\mu}m$, the self-erasing discharge was improved in the sustain period. Also, the $V_S$ and $V_A$ minimum voltage of the CLHS driving method decreased about 9V and 12V compared with those of the normal driving method. Moreover, when the CLHS driving method was applied to the panel with ITO gap of $100{\mu}m$, the luminance and the luminous efficiency increased compared with those of the normal driving method. The luminance and the luminous efficiency greatly increased at the low discharge load. The less discharge load, the higher increase rate of the luminance and the luminous efficiency. Especially, the luminous efficiency at ITO gap of $100{\mu}m$ increased about 26.3% at the discharge load of 4% compared with that at ITO gap of $65{\mu}m$.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 C
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• pp.1755-1758
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• 2004

Misfiring is often observed during the high temperature quality assurancetest of plasma display panel. This limits the productivity of PDP industry. In this paper, experimental observations on the misfiring at high panel temperature have been performed through time dependent discharge light output and static margin measurement. For the high temperature condition, firing voltage increment is found in both surface and facing discharges. This in turn increases lime lag in address discharge, and results m increment of misfiring probability. In order to reduce this kind of misfiring, a new method that applies automatically different slope of ramp erasing pulse on the common electrode according to temperature variation is proposed. The experimental results show that controlling the slope of ramp erasing pulse is quite effective for compensating temperature-dependent variation of reset and address discharge.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.164-170
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• 2004

Misfiring is often observed during the high temperature quality assurance test of plasma display panel. This limits the productivity of PDP industry. In this paper, experimental observations on the misfiring at high panel temperature have been performed through time dependent discharge light output and static margin measurement. For the high temperature condition, firing voltage increment is found in both surface and facing discharges. This in turn increases time lag in address discharge, and results in increment of misfiring probability. In order to reduce this kind of misfiring, a new method that applies automatically different slope of ramp erasing pulse on the common electrode according to temperature variation is proposed. The experimental results show that controlling the slope of ramp erasing pulse is quite effective for compensating temperature-dependent variation of reset and address discharge.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.407-410
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• 2005

For reducing DFC(Dynamic False Contour), we propose a new PDP driving method by rearrangement of sub-fields. The proposed method constructs a frame using 16 sub-fields for expressing 256 gray levels. Although the number of sub-fields increases, the display time increases compared to the conventional 8 sub-fields driving method. This increase in display time is achieved by properly using both selective writing and selective erasing for each sub-field.

• 정보처리학회논문지B
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• 제9B권4호
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• pp.509-516
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• 2002

본 논문에서는 그림, 글자, 표, 직선 등과 같은 다양한 정보를 포함하는 문서 영상 인식에 대한 효율적인 알고리즘을 제안한다. 이 시스템은 문서영상의 기울짐을 보정하기 위한 회전각검출 단계, 불필요한 배경영역을 제거하는 단계, 문서영상에 내재된 각 구성요소를 검출하는 분류 단계로 구성된다. 알고리즘은 문서의 기울어짐에 의해서 발생되는 오류를 최소화하기 위한 회전각 검출과정과 검출된 회전각을 기반으로 문서를 보정하는 전처리단계를 수행한다. 입력된 문서영상의 수평성분과 수직성분만을 이용하여 회전각을 검출하고, 문서의 구성요소 검출과정에서 불필요한 배경영역을 제거함으로써 계산시간을 최소화하였다. 그리고 영상에 내재된 그림영역, 글자영역, 표영역, 직선영역 둥의 다양한 구성요소를 분류한다. 제안한 문서 인식 시스템의 성능 평가를 위해서 다양한 문서영상에 제안한 방법을 적용하고 성공적인 결과를 보인다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2019년도 춘계학술발표대회
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• pp.472-474
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• 2019

Because of the difference in network structure and loss function, Verification and identification models have their respective advantages and limitations for person reidentification (re-ID). In this work, we propose a multi-task network simultaneously computes the identification loss and verification loss for person reidentification. Given a pair of images as network input, the multi-task network simultaneously outputs the identities of the two images and whether the images belong to the same identity. In experiments, we analyze the major factors affect the accuracy of person reidentification. To address the occlusion problem and improve the generalization ability of reID models, we use the Random Erasing Augmentation (REA) method to preprocess the images. The method can be easily applied to different pre-trained networks, such as ResNet and VGG. The experimental results on the Market1501 datasets show significant and consistent improvements over the state-of-the-art methods.

• 전자공학회논문지A
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• 제30A권5호
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• pp.1-15
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• 1993

In DQDB networks, the bandwidth can be increased considerably be using the EN(Erasure Node) algorithms and DR(Destination Release) algorithms. However, the important issue in implementing them is using method of extra capacity fairly. To improve it, this paper proposes AEN(Adaptive Erasure Node) algorithm which erasure function is activated by network traffic load. Its functional architecture consists of SESM, RCSM, LMSM in addition to the basic DQDB state machines (DQSM, RQM). The SESM and RCSM state machines are placed in front of the DQSM and RQM state machines in order for the node to take advantage of the newly cleared slots. This paper also presents some simulation results showing the effect of AEN algorithm on access delay, throughput and segment erasing ratio in the single and multiple priority networks. The results show that the AEN algorithm offer the better performance characteristics than existing algorithms under overload conditions.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.121-122
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• 2000

The understanding of reset scheme is essential for the driving of AC PDP (Plasma Display Panel). The characteristics of reset period of AC PDP was examined with the variation of pulse time and voltage in the ADS (Address Display Separated) driving method presented by Fujitsu,. The addressing characteristics showed drastic change as a function of the erasing time and addressing pulse width. In this paper, these results were explained by the change of wall charge variation, and it was estimated with the currents through each electrode.