• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.26-29
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• 2002

The ramp waveform has recently been introduced to erase wall charges of the previously selected cells for plasma display. However. the ramp waveform can't completely remove wall charges. In this paper. we suggested new erase waveform having a complex with close width pulse and ramp pulse for complete erasing. The erasing margin of suggested waveform is wider than the conventional waveform. Moreover. suggested wave form can reduce the erasing time compared.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.879-882
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• 1999

The effects of the substrate bias on the performance of programming erasing in p-channel flash memory cell have been investigated. It is found that applying positive substrate bias can improve the programming and erasing speed. This improvements can be explained by Substrate Current Induced Hot Electron Injection. From the results, we can confirm that BTB programming method is better in programming and erasing speed than CHE programming method.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.21-27
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• 1999

In this work, single-poly EEPROM was designed and fabricated by using standard $0.8{\mu}m$ CMOS process. From the results of programming and erasing characteristics, it was found that the programming time was smaller than 10ms and the erasing time was about 100ms. To reduce the erasing time, several erasing methods were performed. The S/D erasing method was used to improve the endurance characteristics which was degraded due to electron trapping in programming and erasing cycles. By using the S/D erasing method, the more improved endurance characteristics then conventional one was obtained.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.11a
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• pp.244-247
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• 2020

Data augmentation has been helpful in improving the performance in deep learning, when we have a limited data and random erasing is one of the augmentations that have shown impressive performance in deep learning in multiple domains. But the main issue is that sometime it loses good features when randomly selected region is erased by some random values, that does not improve performance as it should. We target that problem in way that good features should not be lost and also want random erasing at the same time. For that purpose, we introduce new augmentation technique named Intra-Class Random Erasing (ICRE) that focuses on data to learn robust features of the same class samples by randomly exchanging randomly selected region. We perform multiple experiments by using different models including resnet18, VGG16 over variety of the datasets including ESC10, UrbanSound8K. Our approach has shown effectiveness over others methods including random erasing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.395-398
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• 2002

Many research group started study to develope x-ray detector using thin film transistor from 1970. But realization of TFT based x-ray detector development was caused by progress of thin film transistor liquid crystal display(TFTLCD) device technology in 1990. The main current of TFT technology is display device. Research results expend TFT technology field from display device to sensor manufacture technology. These days many research group in the world realize various digital x-ray detector. In this study, We compare discharge erasing method to visible light erasing method in a-Se based digital x-ray detector. Visible light erasing method is known reset process in direct conversion x-ray detector. Digital x-ray detector using visible light erasing method is not adaptive for conventional x-ray device, because of its thickness. And it is not avaliable for real-time imaging for digital fluoroscopy, because of its long reset time. In this study we overcome these limitations and show new idea for real-time imaging method.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.425-428
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• 1998

In this work, single-poly EEPROM has been designed and fabricated by using standard 0.8.mu.m CMOS process. The initial threshold voltage was aobut 0.8V but it increased ot about 6.5V after programming at Vds=11.5V and Vcg=6.5V. After erasing devices at Vs=14.2V, the threshold voltage decreased to about 1.5V. The programming time and erasing trime wree about 6ms. and 100ms. respectively. The erasing time can be reduced by applying a series of shorter erase pulse s instead of a long single erase pulse.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.128-131
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• 2002

In this paper, we used the V-Q Lissajous‘ figure for studying on the plasma discharge characteristics of the 42 inches AC-PDP. From the V-Q Lissajous‘ figure, we could observe exactly the driving conditions that the self-erasing discharge takes place. At the time, the total wall charges lessened by self-erasing discharge was calculated quantitatively. Beside of the just observation of self-erasing discharge and calculation of the charges lessened, we could find out the optimum driving conditions for inducing the maximum wall charges accumulated on the dielectric layer with measuring the Wall voltage from the V-Q Lissajous' figure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.452-458
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• 2022

The electro-thermal erasing (ETE) configuration utilizes Joule heating intentionally generated at word-line (WL). The elevated temperature by heat physically removes stored electrons permanently within a very short time. Though the ETE configuration is a promising next generation NAND flash memory candidate, a consideration of power efficiency and erasing speed with respect to device structure and its scaling has not yet been demonstrated. In this context, based on 3-dimensional (3-D) thermal simulations, this paper discusses the impact of device structure and scaling on ETE efficiency. The results are used to produce guidelines for ETEs that will have lower power consumption and faster speed.

• Science of Emotion and Sensibility
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• v.18 no.2
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• pp.65-74
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• 2015

Nowadays, people start to focus on the value of 'Mindfulness' and 'Slowness', instead of the importance of 'Development' and 'Advancement' in their whole life. According to this background, we attempted to find new research opportunities on User Experience(UX) in usage context of 'Erasing'. Through a interdisciplinary literature review on related works regarding the concept of erasing, we tried to understanding the meaning of erasing within the perspective of philosophy, psychology, and human-computer interaction(HCI). We also conducted the contextual inquiry, one of the qualitative research methods to examine the actual usage context and the user's experience, with 79 users who were required to erase something in three usage contexts, including Paper-Eraser condition, Computer-Keyboard condition, and Tablet PC condition. The results indicate that it is important to provide not only effective erasing but also satisfaction for users in the usage-context of erasing. From these attempts, we expect that our findings will be helpful to understand the meaning of the erasing in academic and practical fields.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.48-51
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• 2000

We proposed the new driving waveform which has changed the waveform of sustain division to improve luminous efficiency in plasma display panel. This sustain waveform is to add the ramp to the rectangular waveform, resulting in self-erasing discharge in the falling edge region. The proposed waveform has improved the luminous efficiency of 30％ even in low driving frequency(25kHz), whereas the conventional driving waveform using the self-erasing discharge can improve the luminous efficiency only in high driving frequency( >150kHz). Front the results of this paper, we hope that the variety study on frequency and duty ratio, ramp waveform will increase the luminous efficiency.