• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.25-29
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• 2021

This paper demonstrates the utility of the Ni-Pd and carbon-nanotube (Ni-Pd-CNT)-based nanoalloy to improve the α-Ga₂O₃ crystal quality using the halide-vapor-phase epitaxy (HVPE) method. As result, the overall thickness of the α-Ga₂O₃ epitaxial layer increased from a Ni electroless plating time of 40 s to 11 ㎛ after growth. In addition, the surface morphologies of the α-Ga₂O₃ epilayers remained flat and crack-free. The full-width half-maximum results of the X-ray diffraction analysis revealed that the ($10{\bar{1}}4$) diffraction patterns decreased with increasing nominal thickness.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.340-340
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• 2002

In an effort to develop alternative single buffer layer technology for YBa$_2$Cu$_3$O$_{7-{\delta}}$ (YBCO) coated conductors, we have investigated both LaMnO$_3$, (LMO) and La$_2$Zr$_2$O$_{7}$ (LZO) as potential buffer layers. High-quality LMO films were grown directly on textured Ni and Ni-W (3%) substrates using rf magnetron sputtering. Highly textured LZO buffers were grown on textured Ni substrates using sol-gel alkoxide processing route. YBCO films were then grown on both LMO and LZO buffers using pulsed laser deposition. Detailed X-ray studies have shown that YBCO films were grown on both LMO and LZO layers with a single epitaxial orientation. A high J$_{c}$ of over 1 MA/cm$^2$ at 77 K and self-field was obtained on YBCO films grown on both LMO-buffered Ni or Ni-W substrates, and also on LZO-buffered Ni substrates. We have identified LaMnO$_3$ as a good diffusion barrier layer for Ni and it also provides a good template for growing high current density YBCO films. Similarly we have also demonstrated the growth of high J$_{c}$ YBCO films on all solution buffers. We will discuss in detail about our buffer deposition processes. processes.s.s.s.s.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2001.11a
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• pp.68-68
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• 2001

Thin films of polycrystalline silicon (poly-Si) is a promising material for use in large-area electronic devices. Especially, the poly-Si can be used in high resolution and integrated active-matrix liquid-crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs) because of its high mobility compared to hydrogenated _amorphous silicon (a-Si:H). A number of techniques have been proposed during the past several years to achieve poly-Si on large-area glass substrate. However, the conventional method for fabrication of poly-Si could not apply for glass instead of wafer or quartz substrate. Because the conventional method, low pressure chemical vapor deposition (LPCVD) has a high deposition temperature ($600^{\circ}C-1000^{\circ}C$) and solid phase crystallization (SPC) has a high annealing temperature ($600^{\circ}C-700^{\circ}C$). And also these are required time-consuming processes, which are too long to prevent the thermal damage of corning glass such as bending and fracture. The deposition of silicon thin films on low-cost foreign substrates has recently become a major objective in the search for processes having energy consumption and reaching a better cost evaluation. Hence, combining inexpensive deposition techniques with the growth of crystalline silicon seems to be a straightforward way of ensuring reduced production costs of large-area electronic devices. We have deposited crystalline poly-Si thin films on soda -lime glass and SiOz glass substrate as deposited by PVD at low substrate temperature using high power, magnetron sputtering method. The epitaxial orientation, microstructual characteristics and surface properties of the films were analyzed by TEM, XRD, and AFM. For the electrical characterization of these films, its properties were obtained from the Hall effect measurement by the Van der Pauw measurement.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.134-138
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• 2023

This study focuses on the analysis of the results of computational fluid dynamics simulations of mist-chemical vapor deposition for the growth of an epitaxial wafer in power semiconductor technology using artificial intelligence techniques. The conventional approach of predicting the uniformity of the deposited layer using computational fluid dynamics and design of experimental takes considerable time. To overcome this, artificial intelligence method, which is widely used for optimization, automation, and prediction in various fields, was utilized to analyze the computational fluid dynamics simulation results. The computational fluid dynamics simulation results were analyzed using a supervised deep neural network model for regression analysis. The predicted results were evaluated quantitatively using Euclidean distance calculations. And the Bayesian optimization was used to derive the optimal condition, which results obtained through deep neural network training showed a discrepancy of approximately 4% when compared to the results obtained through computational fluid dynamics analysis. resulted in an increase of 146.2% compared to the previous computational fluid dynamics simulation results. These results are expected to have practical applications in various fields.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.5
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• pp.442-453
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• 2023

Tandem or multijunction solar cells (MJSCs) can convert sunlight into electricity with higher efficiency (η) than single junction solar cells (SJSCs) by dividing the solar irradiance over sub-cells having distinct bandgaps. The efficiencies of various common SJSC materials are close to the edge of their theoretical efficiency and hence there is a tremendous growing interest in utilizing the tandem/multijunction technique. Recently, III-V materials integration on a silicon substrate has been broadly investigated in the development of III-V on Si tandem solar cells. Numerous growth techniques such as heteroepitaxial growth, wafer bonding, and mechanical stacking are crucial for better understanding of high-quality III-V epitaxial layers on Si. As the choice of growth method and substrate selection can significantly impact the quality and performance of the resulting tandem cell and the terminal configuration exhibit a vital role in the overall proficiency. Parallel and Series-connected configurations have been studied, each with its advantage and disadvantages depending on the application and cell configuration. The optimization of both growth mechanisms and terminal configurations is necessary to further improve efficiency and lessen the cost of III-V on Si tandem solar cells. In this review article, we present an overview of the growth mechanisms and terminal configurations with the areas of research that are crucial for the commercialization of III-V on Si tandem solar cells.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.339-339
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• 2002

In the RABiTS approach to coated conductor development, successful (both economic and technological) depends on the refinement and optimization of each of three important components: the metal tape substrate, the buffer layer(s), and the HTS layer. Here we will report on the ORNL approach and progress in each of these areas. - Most applications will require metal tapes with low magnetic hysteresis, mechanical strength, and excellent crystalline texture. Some of these requirements are competing. We report on progress in obtaining a good combination of these characteristics on metal alloys of Ni-Cr and Ni-W. - The deposition of appropriate buffer layers is a crucial step. Recently, base research has shown that the presence of a stable sulfur superstructure present on the metal surface is needed for the nucleation and epitaxial growth of vapor-deposited seed buffer layers such as YSZ, CeO$_2$ and SrTiO$_3$. We report on the details and control of this superstructure for nickel tapes, as well as recent results for Cu and Ni-13%Cr. - Processes for deposition of the HTS coating must economically provide large values of the figure-of-merit for conductors, current x length. At ORNL, we have devoted efforts to a precursor/post-annealing approach to YBCO coatings, for which the deposition and reaction steps are separate. We describe motivation for and progress toward developing this approach. - Finally, we address some issues for the implementation of coated conductors in real applications, including the need for texture control and electrical stabilization of the HTS coating.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.20-20
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• 2003

We developed 30 ㎽-AlInGaN based violet laser diodes. The fabrication procedures of the laser diodes are described as follows. Firstly, GaN layers having very low defect density were grown on sapphire substrates by lateral epitaxial overgrowth method. The typical dislocation density was about 1-3$\times$10$^{6}$ /$\textrm{cm}^2$ at the wing region. Secondly, AlInGaN laser structures were grown on LEO-GaN/sapphire substrates by MOCVD. UV activation method, instead of conventional annealing, was conducted to achieve good p-type conduction. Thirdly, ridge stripe laser structures were fabricated. The cavity mirrors were formed by cleaving method. Three pairs of SiO$_2$ and TiO$_2$ layers were deposited on the rear facet for mirror coating. Lastly, laser diode chips were mounted on AlN submount wafers by epi-down bonding method. The lifetime of the laser diodes was over 10,000 hrs at room temperature under automatic power controlled condition. We expect the performance of the LDs to be improved by the optimization of the growth and fabrication process. The detailed characteristics and important issues of the laser diodes will be discussed at the conference.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.1
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• pp.70-75
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• 1997

An improved technique based upon an electron beam evaporation system has been developed to prepare cubic thin films In crystalline semiconductors. Zinc blonde CdSe epilayers were grown on GaAs(100) substrate by an e-beam evaporation method. The lattice parameter obtained from (400) reflection is $6.077\AA$, which is in excellent agreement with the value reported in the literature for zinc blonde CdSe. The orientation of the as-grown CdSe epilayer is determined by electron channeling patterns. The crystallinity of epitaxial CdSe layers were investigated on the double crystal X-ray rocking curve. The carrier concentration and mobility of epilayers deduced by Hall effect measurement are about $10^{18}{\textrm}{cm}^{-3}$, $10^2\textrm{cm}^2/V{\cdot}sec$ at room temperature, respectively. The photocurrent spectrum peak of the epilayer at 30 K exhibits a sharp change at 1.746 eV due to the free exciton of cubic CdSe.

• Korean Journal of Materials Research
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• v.3 no.6
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• pp.645-651
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• 1993

The growth of semi-insulating(SI) high resistant undoped GaAs epilayer has been studied to solve the problems ocurring when GaAs IC is fabricated by the widely used ion implantation directly into the SI GaAs substrate. The EPD ditribution of the SI substrates has been examined, and the suitability of the buffer layers grown by MOCVD and MBE, respectively, has been tested for IC fabrication through leakage current measurement. IJngated FET has been fabricated on the SI epilayer and leakage current through the buffer layer has been measured. In the case of MOCVD grown 1$\mu\textrm{m}$-thick buffer layer, the leakage current is as small as about 270nA/mm, and this value does not affect the pinch-off of FET. In this case, the epilayer quality is affected by the substrate defects because the leakage current distribution is coincided with the EPD distribution of the SI substrate. The 2$\mu\textrm{m}$-thick buffer layer grown by MBE, however, has the better quality, and shows the lower leakage current(40nA/mrn) and higher uniformity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1281-1286
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• 2006

We have used the silicon-carbide(4H-SiC) instead of conventional silicon materials to develope of the planar junction barrier schottky rectifier for ultra high breakdown voltage(1,200 V grade). The substrate size is 2 inch wafer, Its concentration is $3*10^{18}/cm^{3}$ of $n^{+}-$type, thickness of epitaxial layer $12{\mu}m$ conentration is $5*10^{15}cm^{-3}$ of n-type. The fabticated devices are junction barrier schottky rectifier, The guard ring for improvement of breakdown voltage is designed by the box-like impurity of boron, the width and space of guard ring was designed by variation. The contact metals to rectify were used by the $Ni(3,000\:{\AA})/Au(2,000\:{\AA})$. As a results, the on-state voltage is 1.26 V, on-state resistance is $45m{\Omega}/cm^{3}$, maximum value of improved reverse breakdown voltage is 1180V, reverse leakage current density is $2.26*10^{-5}A/CM^{3}$. We had improved the measureme nt results of the electrical parameters.