• 한국안광학회지
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• 제9권1호
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• pp.35-41
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• 2004

IV-VI족 화합물인 PbSnSe는 흥미 있는 물리적 특성을 가지고 있는 화합물 반도체로써 본 실험에서는 HWE 방법으로 성장시킨 PbSnSe 박막에 대한 특성을 조사하였다. 원료부와 열벽부 그리고 기판의 온도를 변화시키며 단결정 박막을 성장시켰다. Rutherford back scattering (RBS)을 측정하여 Pb:Sn:Se의 조성비를 확인하였다. 특히 좁은 에너지 대역을 측정하기에 매우 용이한 Fourier transform infra red (FT-IR)측정 장치를 이용하여 에너지 갭을 측정하였다. 박막의 표면 상태는 atomic force microscopy (AFM) 사진과 주사 전자 현미경 (SEM) 사진으로 관찰하여 결정구조와 성장 용도와의 연관성을 조사하였다. 광학 상수는 Spectroscopic ellipsometry (SE) 방법을 이용하여 박막의 광학 상수를 측정했다. PbSnSe 화합물 에피층 시료의 굴절률(n), 유전상수(${\varepsilon}$), 반사율(R) 그리고 흡수 계수(${\alpha}$)등 광학상수를 측정하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.350-353
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• 2002

High voltage SiC Schottky barrier diodes with field plate structure have been fabricated and characterized. N-type 4H-SiC wafer with an epilayer of ∼10$\^$15/㎤ doping level was used as a starting material. Various Schottky metals such as Ni, Pt, Ta, Ti were sputtered and thermally-evaporated on the low-doped epilayer. Ohmic contact was formed at the backside of the SiC wafer by annealing at 950$^{\circ}C$ for 90 sec in argon using rapid thermal annealer. Field oxide of 550${\AA}$ in thickness was formed by a wet oxidation process at l150$^{\circ}C$ for 3h and subsequently heat-treated at l150$^{\circ}C$ for 30 min in argon for improving oxide quality. The turn-on voltages of the Ni/4H-SiC Schottky diode was 1.6V which was much higher than those of Pt(1.0V), Ta(0.7V) and Ti(0.7). The voltage drop was measured at the current density of 100A/$\textrm{cm}^2$ showing 2.1V for Ni Schottky diode, 1.45V for Pt 1.35V, for Ta, and 1.25V for Ti, respectively. The maximum reverse breakdown voltage was measured 1100V in the file plated Schottky diodes with 101an thick epilayer.

• 전자통신동향분석
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• 제3권4호
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• pp.3-12
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• 1988

Epilayer growing process has been recognized as a key technology for successful GaAs based devices and integrations. These may include HEMT, multiple quantum well structures, band gap engineering, and quantum confinement heterostructures. The fabrication of epilayers in these devices must meet very stringent requirements in terms of crystallinity, composition, film thickness and interface quality. In particular, the quality of interfaces is getting more important because the film thickness, and flatness, roughness and stability at interface of ultrathin films cause critical effects on the device performance. This article reviews the current status of modern epitaxial techniques which have been developed in the last few years. First, the new techniques PLE, GI, MEE, TSL based on MBE technique will be reviewed and their technical importance will be stressed. Secondly, MOMBE, GSMBE, CBE which combine the advantages of MBE and MOCVD will also be discussed. Thirdly, the new sophisticated epitaxial technique, ALE, of which mechanism is totally different from others, will also be reviewed. Finally, areas which should be exploited more extensively to accomplish these techniques will be addressed.

• 한국안광학회지
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• 제7권2호
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• pp.209-215
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• 2002

본 실험에서는 HWE 방법으로 성장시킨 SnSe 단결정 박막에 대한 특성을 조사하였다. 성장된 박막의 결정 구조와 격자 상수를 알아보기 위하여 X-ray diffraction(XRD)에 의한 회절 패턴을 측정하고, 단결정 박막의 결정성을 확인하기 위하여 double crystal X-ray diffraction(DCXRD)에 의한 회절 패턴을 측정하여, 원료부와 열벽부 그리고 기판의 온도 변화에 따른 반치폭을 알아보았다. Rutherford back scattering(RBS)을 측정하여 Sn과 Se의 조성비를 확인하고, 실험값과 이론값의 차이를 조사하였다. 박막의 표면 상태는 atomic force microscopy(AFM) 사진과 주사 전자 현미경(SEM) 사진으로 관찰하여 결정구조와 성장 온도와의 연관성을 조사하였다. 광학 상수는 Spectroscopic Ellipsometry(SE) 방법을 이용하여 단결정 박막의 굴절률(n), 유전상수(${\varepsilon}$), 반사율(R) 그리고 흡수 계수(${\alpha}$) 등 광학 상수를 측정했다.

• Applied Microscopy
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• 제26권4호
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• pp.479-487
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• 1996

Thin epilayer structures of GaAs/AlAs/InGaAs, grown by Molecular Beam Epitaxy, were investigated by high resolution transmission electron microscopy, Image in the [110] zone axis was taken and compared with the calculated images. The supercell structure which contains GaAs, AlAs and InGaAs layers was designed and was employed in the image calculation with MacTempas computer program. Good agreement was shown between experimental image and a set of calculated images with varying defocus and sample thickness.

• 한국공작기계학회논문집
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• 제11권6호
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• pp.111-117
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• 2002

The high quality and a nearly stoichometric growth of $Cd_{1-y} Zn_y$/Te(y＝0.04) epilayers have been successfully grown on GaAs substrate by hot wall epitaxy (HWE) by optimizing the growth condition including the preheating treatment and Cd reservoir temperature. The relationship between quality and thickness was examined and best value of FWHM from X-ray rocking curve of 121 arcsec are obtained. Also, emission peaks related to the recombination of free excitons such as the ground state and the first excited state were observed in the PL spectrum at 4.2K. The ($A^0$, X) emission related to Cd vacancy and deep level emission was not measured. These results indicated that the grown CZT/GaAs epilayer was high qualify and purity.

• Electronic Materials Letters
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• 제14권6호
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• pp.784-792
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• 2018

In this letter, a standard deviation based optimization technique has been applied on High Resolution X-ray Diffraction symmetric and asymmetric scan results to accurately determine the Aluminum molar fraction and lattice relaxation of Molecular Beam Epitaxy grown compositionally graded Aluminum Gallium Nitride (AlGaN)/Aluminum Nitride/Gallium Nitride (GaN) heterostructures. Mathews-Blakeslee critical thickness model has been applied in an alternative way to determine the partially relaxed AlGaN epilayer thicknesses. The coupling coefficient determination has been presented in a different perspective involving sample tilt method by off set between the asymmetric planes of GaN and AlGaN. Sample tilt is further increased to determine mosaic tilt ranging between $0.01^{\circ}$ and $0.1^{\circ}$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• 한국표면공학회지
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• 제43권4호
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• pp.170-175
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• 2010

The GaAs epitaxial layers were grown on Si(100) substrates by molecular beam epitaxy(MBE) using the two-step method. The Si(100) substrates were cleaned with different surface cleaning method of vacuum heating, As-beam, and Ga-beam at the substrate temperature of $800^{\circ}C$. Growth temperature and thickness of the GaAs epitaxial layer were $800^{\circ}C$ and 1 ${\mu}m$, respectively. The surface structure and epitaxial growth were observed by reflection high-energy electron diffraction(RHEED) and scanning electron microscope(SEM). Just surface structure of the Si(100) substrate cleaned by Ga-beam at $800^{\circ}C$ shows double domain ($2{\times}1$). RHEED patterns of the GaAs epitaxial layers grown on Si(100) substrates with cleaning method of vacuum heating, As-beam, and Ga-beam show spot-like, ($2{\times}4$) with spot, and clear ($2{\times}4$). From SEM, it is found that the GaAs epitaxial layers grown on Si(100) substrates with Ga-beam cleaning has a high quality.

• 한국전기전자재료학회논문지
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• 제22권9호
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• pp.737-740
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.