• Journal of Korean Ophthalmic Optics Society
• /
• v.9 no.1
• /
• pp.35-41
• /
• 2004

This study investigated the crystal growth, crystalline structure and the basic optical properties of $PbSnSe/BaF_2$ epilayers. The PbSnSe epilayer was grown on $BaF_2$(111) insulating substrates using a hot wall epitaxy (HWE) technique. It was found from the analysis of X-ray diffraction patterns that $PbSnSe/BaF_2$ epilayer was grown single crystal with a rock-salt structure oriented along [111] the growth direction. Using Rutherford back scattering, the atomic ratios of the PbSnSe was found to be proper stoichiometric. The best values for the full width at half maximum (FWHM) of the DCXRD was 162 arcsec for PbSnSe epilayer. The epilayer-thickness dependence of the FWHM of the DCXRD shows that the quality of the $PbSnSe/BaF_2$ is as expected. The dielectric function ${\varepsilon}(E)$ of a semiconductor is closely related to its electronic energy band structure and such relation can be drawn from features around the critical points(CPs) in the optical spectra. The real and imaginary parts(${\varepsilon}1$ and ${\varepsilon}2$) of the dielectric function ${\varepsilon}$ of PbSe were measured, and the observed spectra reveal distinct structures at energies of the E1, E2 and E3 CPs. These data are analyzed using a theoretical model known as the model dielectric function (MDF). The optical constants related to dielectric function such as the complex refractive index ($n^*=n+ik$), absorption coefficient (${\alpha}$) and normal-incidence reflectivity (R) are also presented for $PbSnSe/BaF_2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.350-353
• /
• 2002

High voltage SiC Schottky barrier diodes with field plate structure have been fabricated and characterized. N-type 4H-SiC wafer with an epilayer of ∼10$\^$15/㎤ doping level was used as a starting material. Various Schottky metals such as Ni, Pt, Ta, Ti were sputtered and thermally-evaporated on the low-doped epilayer. Ohmic contact was formed at the backside of the SiC wafer by annealing at 950$^{\circ}C$ for 90 sec in argon using rapid thermal annealer. Field oxide of 550${\AA}$ in thickness was formed by a wet oxidation process at l150$^{\circ}C$ for 3h and subsequently heat-treated at l150$^{\circ}C$ for 30 min in argon for improving oxide quality. The turn-on voltages of the Ni/4H-SiC Schottky diode was 1.6V which was much higher than those of Pt(1.0V), Ta(0.7V) and Ti(0.7). The voltage drop was measured at the current density of 100A/$\textrm{cm}^2$ showing 2.1V for Ni Schottky diode, 1.45V for Pt 1.35V, for Ta, and 1.25V for Ti, respectively. The maximum reverse breakdown voltage was measured 1100V in the file plated Schottky diodes with 101an thick epilayer.

• Electronics and Telecommunications Trends
• /
• v.3 no.4
• /
• pp.3-12
• /
• 1988

Epilayer growing process has been recognized as a key technology for successful GaAs based devices and integrations. These may include HEMT, multiple quantum well structures, band gap engineering, and quantum confinement heterostructures. The fabrication of epilayers in these devices must meet very stringent requirements in terms of crystallinity, composition, film thickness and interface quality. In particular, the quality of interfaces is getting more important because the film thickness, and flatness, roughness and stability at interface of ultrathin films cause critical effects on the device performance. This article reviews the current status of modern epitaxial techniques which have been developed in the last few years. First, the new techniques PLE, GI, MEE, TSL based on MBE technique will be reviewed and their technical importance will be stressed. Secondly, MOMBE, GSMBE, CBE which combine the advantages of MBE and MOCVD will also be discussed. Thirdly, the new sophisticated epitaxial technique, ALE, of which mechanism is totally different from others, will also be reviewed. Finally, areas which should be exploited more extensively to accomplish these techniques will be addressed.

• Journal of Korean Ophthalmic Optics Society
• /
• v.7 no.2
• /
• pp.209-215
• /
• 2002

This study investigated the crystal growth, crystalline structure and the basic optical properties of $SnSe/BaF_2$ epilayers. The SnSe epilayer was grown on $BaF_2$(111) insulating substrates using a hot wall epitaxy(HWE) technique. It was found from the analysis of X-ray diffraction patterns that $SnSe/BaF_2$ epilayer was growing to single crystal with orthorhombic structure oriented [111] along the growth direction. Using Rutherford back scattering(RBS), the atomic ratios of the SnSe was found to be stoichiometric, almost 50 : 50. The best values for the full width at half maximum (FWHM) of the DCXRD was 163 arcsec for SnSe epilarer. The epilayer-thickness dependence of the FWHM of the DCXRD shows that the quality of the $SnSe/BaF_2$ is as expected. The dielectric function ${\varepsilon}$(E) of a semiconductor is closely related to its electronic energy band structure and such relation can be drawn from features around the critical points in the optical spectra. The real and imaginary parts(${\varepsilon}_1$ and ${\varepsilon}_2$) of the dielectric function ${\varepsilon}$ of SnSe were measured. These data are analyzed using a theoretical model known as the model dielectric function(MDF). The optical constants related to dielectric function such as the complex refractive index(n*-n+ik), absorption coefficient (${\alpha}$) and normal- incidence reflectivity (R) are also presented for $SnSe/BaF_2$.

• Applied Microscopy
• /
• v.26 no.4
• /
• pp.479-487
• /
• 1996

Thin epilayer structures of GaAs/AlAs/InGaAs, grown by Molecular Beam Epitaxy, were investigated by high resolution transmission electron microscopy, Image in the [110] zone axis was taken and compared with the calculated images. The supercell structure which contains GaAs, AlAs and InGaAs layers was designed and was employed in the image calculation with MacTempas computer program. Good agreement was shown between experimental image and a set of calculated images with varying defocus and sample thickness.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.11 no.6
• /
• pp.111-117
• /
• 2002

The high quality and a nearly stoichometric growth of $Cd_{1-y} Zn_y$/Te(y＝0.04) epilayers have been successfully grown on GaAs substrate by hot wall epitaxy (HWE) by optimizing the growth condition including the preheating treatment and Cd reservoir temperature. The relationship between quality and thickness was examined and best value of FWHM from X-ray rocking curve of 121 arcsec are obtained. Also, emission peaks related to the recombination of free excitons such as the ground state and the first excited state were observed in the PL spectrum at 4.2K. The ($A^0$, X) emission related to Cd vacancy and deep level emission was not measured. These results indicated that the grown CZT/GaAs epilayer was high qualify and purity.

• Electronic Materials Letters
• /
• v.14 no.6
• /
• pp.784-792
• /
• 2018

In this letter, a standard deviation based optimization technique has been applied on High Resolution X-ray Diffraction symmetric and asymmetric scan results to accurately determine the Aluminum molar fraction and lattice relaxation of Molecular Beam Epitaxy grown compositionally graded Aluminum Gallium Nitride (AlGaN)/Aluminum Nitride/Gallium Nitride (GaN) heterostructures. Mathews-Blakeslee critical thickness model has been applied in an alternative way to determine the partially relaxed AlGaN epilayer thicknesses. The coupling coefficient determination has been presented in a different perspective involving sample tilt method by off set between the asymmetric planes of GaN and AlGaN. Sample tilt is further increased to determine mosaic tilt ranging between $0.01^{\circ}$ and $0.1^{\circ}$.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.274-283
• /
• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• Journal of the Korean institute of surface engineering
• /
• v.43 no.4
• /
• pp.170-175
• /
• 2010

The GaAs epitaxial layers were grown on Si(100) substrates by molecular beam epitaxy(MBE) using the two-step method. The Si(100) substrates were cleaned with different surface cleaning method of vacuum heating, As-beam, and Ga-beam at the substrate temperature of $800^{\circ}C$. Growth temperature and thickness of the GaAs epitaxial layer were $800^{\circ}C$ and 1 ${\mu}m$, respectively. The surface structure and epitaxial growth were observed by reflection high-energy electron diffraction(RHEED) and scanning electron microscope(SEM). Just surface structure of the Si(100) substrate cleaned by Ga-beam at $800^{\circ}C$ shows double domain ($2{\times}1$). RHEED patterns of the GaAs epitaxial layers grown on Si(100) substrates with cleaning method of vacuum heating, As-beam, and Ga-beam show spot-like, ($2{\times}4$) with spot, and clear ($2{\times}4$). From SEM, it is found that the GaAs epitaxial layers grown on Si(100) substrates with Ga-beam cleaning has a high quality.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.9
• /
• pp.737-740
• /
• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.