• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.82-90
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• 2011

Because of the development of Smart phone devices, the demands of high performance FPU(Floating-point Unit) becomes increasing. Therefore, we propose the high-speed single-/double-precision FPU design that includes an elementary add/sub unit and improved multiplier and compare and convert units. The most commonly used add/sub unit is optimized by the parallel rounding unit. The matrix operation is used in complex calculation something like a graphic calculation. We designed the Multiply-Add Fused(MAF) instead of multiplier to calculate the matrix more quickly. The branch instruction that is decided by the compare operation is very frequently used in various programs. We bypassed the result of the compare operation before all the pipeline processes ended to decrease the total execution time. And we included additional convert operations that are added in IEEE754-2008 standard. To verify our RTL designs, we chose four hundred thousand test vectors by weighted random method and simulated each unit. The FPU that was synthesized by Samsung's 45-nm low-power process satisfied the 600-MHz operation frequency. And we confirm a reduction in area by comparing the improved FPU with the existing FPU.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• 대한공업교육학회지
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• v.38 no.2
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• pp.195-217
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• 2013

The purpose of this study was to develop educational programs of STEAM-based project under the theme of "Photography of Earth" for the circle activities of the creative experiential activity, to be applied this program to them and to identify technology subject self-efficacy and change in attitude toward engineering. In order to achieve the research objectives, this program was applied to middle school student in Cheonan, STEAM-based circle during 9 class instruction. The results of this study are as follows. First, the STEAM program contents for circle activities were selected through utilizing a five-stage design model(preparation, design, development, implementation and evaluation) and analyzing the curriculum. After that we have developed a teaching plan, STEAM-Story, student activity sheets from the viewpoint of cultural fusion and have applied the circle activities of the creative experiential Activity during 4 months. Second, The result of the test(pre- and post-test) about STEAM program that has been developed were different about technology subject self-efficacy and attitude toward engineering. Therefore, we have verified that the effect of the STEAM-based project under the theme of "Photography of Earth" for the circle activities on the attitudes toward engineering and self-efficacy in middle school is effective.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.596-601
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• 2011

In this paper, we propose a fast depth-image-based rendering method to generate a virtual view image in real-time using a graphic processor unit (GPU) for a 3D broadcasting system. Before the transmission, we encode the input 2D+depth video using the H.264 coding standard. At the receiver, we decode the received bitstream and generate a stereo video using a GPU which can compute in parallel. In this paper, we apply a simple and efficient hole filling method to reduce the decoder complexity and reduce hole filling errors. Besides, we design a vertical parallel structure for a forward mapping process to take advantage of the single instruction multiple thread structure of GPU. We also utilize high speed GPU memories to boost the computation speed. As a result, we can generate virtual view images 15 times faster than the case of CPU-based processing.

• KIPS Transactions on Software and Data Engineering
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• v.4 no.3
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• pp.135-142
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• 2015

As the importance of software to society has grown, more and more schools worldwide teach coding basics in the classroom. Despite the rapid spread of coding instruction in grade schools, experience in the classroom is certainly limited because there is a gap between the curriculum and the existing computing environment such as the mobile and cloud computing. We propose an approach to fill this gap by using a mobile environment and the robot on the cloud-based platform for effective teaching. In this paper, we propose an architecture called Cloudboard that enables knowledge sharing and collaboration among knowledge providers in the cloud-based robot platforms. We also describe five representative architectural patterns that are referenced and analyzed to design the Cloudboard architecture. Our early experimental results show that the Cloudboard can be effective in the development of collective robotic systems.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.135-141
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• 2020

Today, CPUs in general-purpose computers such as servers, desktops and laptops, as well as home appliances and embedded systems, consist mostly of multicore processors. In order to improve performance, it is required to use an out-of-order execution processor by Tomasulo algorithm as each core processor. An out-of-order execution processor with Tomasulo algorithm can execute the available instructions in any order and perform speculation in order to reduce control dependencies. Therefore, the performance of an out-of-order execution processor can be significantly improved compared to an in-order execution processor. In this paper, an out-of-order execution processor using Tomasulo algorithm and ARM instruction set is designed using VHDL record data types and simulated by GHDL. As a result, it is possible to successfully perform operations on programs written in ARM instructions.

• Journal of Software Assessment and Valuation
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• v.16 no.2
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• pp.1-8
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• 2020

The similarity detection to plagiarism or duplication of computer programs requires a different type of analysis methods and tools according to the programming language used in the implementation and the sort of code to be analyzed. In recent years, the similarity appraisal for the object code in the embedded system, which requires a considerable resource along with a more complicated procedure and advanced skill compared to the source code, is increasing. In this study, we described a method for analyzing the similarity of functional units in the assembly language through the conversion of object code using the reverse engineering approach, such as the reverse assembly technique to the object code. The instruction and operand table for comparing the similarity is generated by using the syntax analysis of the code in assembly language, and a tool for detecting the similarity is designed.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.1-10
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• 2012

This paper proposes design space exploration methodology of many-core processors including multimedia specific instructions to support high-performance and low power ultrasound imaging for portable devices. To explore the impact of multimedia instructions, we compare programs using multimedia instructions and baseline programs with a same many-core processor in terms of execution time, energy efficiency, and area efficiency. Experimental results using a $256{\times}256$ ultrasound image indicate that programs using multimedia instructions achieve 3.16 times of execution time, 8.13 times of energy efficiency, and 3.16 times of area efficiency over the baseline programs, respectively. Likewise, programs using multimedia instructions outperform the baseline programs using a $240{\times}320$ image (2.16 times of execution time, 4.04 times of energy efficiency, 2.16 times of area efficiency) as well as using a $240{\times}400$ image (2.25 times of execution time, 4.34 times of energy efficiency, 2.25 times of area efficiency). In addition, we explore optimal PE architecture of many-core processors including multimedia instructions by varying the number of PEs and memory size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1710-1714
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• 2010

The budget for the acquisition and R&D for the national defence systems has come out of tax payers' pockets. On the other hand, the weapon systems become more complex and thus the underlying costs tend to increase continuously. As such, the need for efficiently managing the budget has drastically increased. In accordance with this necessity, the Defence Acquisition Program Administration (DAPA) of Korea has issued the instruction No.65 dictating that systems engineering (SE) must be applied when weapon systems are acquired or developed in Korea. Specifically, a list of the products that should be generated from the acquisition programs is provided. The problem is that the unexperienced companies in the defence systems industry cannot easily know how to approach the new regulation. The purpose of this study is to devise a possible remedy to solve the problem. To do so, we first review the list of the products that are required by DAPA. Then, an appropriate systems engineering processes is studied for each product. Then, a necessary link between each product and SE process activity is identified and summarized. The result obtained may be useful as a stepping stone to develop more efficient method for the list of the products.

• Korean Journal of Construction Engineering and Management
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• v.14 no.4
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• pp.108-117
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• 2013

The domestic CM business market has continued to grow, but its size is relatively small yet in comparison with the total size of the domestic construction industry. Evaluation of CM projects was conducted through questionnaire surveys. Both clients and CM firms showed positive satisfaction levels. Nevertheless, the clients' satisfaction levels were relatively low in safety management, cost management, and document and information management. Superior areas of CM tasks were time management and recovery scheduling, quality control and technical instruction, and design value engineering. On the other hand, inferior areas of CM tasks were claim analysis and dispute resolution, cost estimation, and life cycle costing. Both entities have agreed with the positive effects of CM involvement in terms of cost saving, time reduction, quality improvement, and safety incidents prevention to at least 0~5% extent.