• Journal of The Korean Association of Information Education
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• v.7 no.3
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• pp.263-274
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• 2003

Web based instruction (WBI) has been widely used thesedays because the web has various advantages for instruction. However, most of current WBI systems do not support various requirements from students. It is because of the lack of research for structural instruction method. This paper presents a new method of WBI and designs an instruction model to support various requirements from students by implementing dynamic WBI system using JSP to solve current WBI problems. The developed WBI system uses multimedia based instructions. The implemented system focused on the practical instruction by providing the functions of listening, homework, and test on web site. For the similar effects as in the classroom, it supports functions of electronic white board and multimedia data which is consisted of high-quality sound and video data with high degree of compression. Furthermore, the system supports that instructors can design a test using three kinds of basic forms, a multiple-choice test, brief-answer test, essay test, and evaluate the tests easily. It also supports easy management for homework, lecture registration, and many school affairs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.3
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• pp.411-417
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• 2018

This paper proposes and implements an on-line instruction manual system which can generate the instruction manual page for the target device at the smartphone on the spot. The instruction manual app. on smartphone scans a QR code or reads NFC tag attached in the instruction manual management module embedded in the target device, and receives instruction manual data from the instruction manual management module through the Bluetooth communications and finally shows the refined instruction manual pages on the smartphone display using a Web-based templates. For the evaluation we embedded the instruction manual management module for an industrial generator with its instruction manual data. Assuming a circumstance of blackout we show that the proposed system can reduce the repair work within two steps compared to three steps in the existing one without the proposed system.

• Journal of IKEEE
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• v.12 no.2
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• pp.118-123
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• 2008

The Khronos group releases OpenGL ES 2.0 API specification bringing streamlined shader programming to graphics processor of embedded system. For this reason, the mobile devices have need of graphics processor for supporting a OpenGL ES 2.0 API. We need to extend instruction`s length to support OpenGLES 2.0 API, so it needs more memory size. In this paper, we propose a new instruction format that offers availability for use the instructions. This proposed instruction adopt a variable length method and unit instruction architecture. This proposed instruction architecture that support to OpenGLES 2.0 API has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of Engineering Education Research
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• v.19 no.2
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• pp.76-82
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• 2016

The purpose of this study is to identify core elements required of instruction consulting and to develop a systematic consulting procedure for successful Flipped Learning. The main contents of this study to achieve its purpose are as follows. First, core elements required of consulting are deduced by analyzing cases of instruction implemented with Flipped Learning. Second, consulting procedure is constructed based on core consulting elements of Flipped Learning. Based on the study results, the 3P process is suggested as the elements and procedure of instruction consulting for Flipped Learning. The 3P process has the following characteristics. The first stage Preparation involves guiding students to have an objective viewpoint about the lesson beginning with building a relationship with the instructor. Also, a lesson plan and source materials for lesson are selected and developed. The second stage Performance involves implementing lesson coaching oriented towards cooperative problem-solving to find better direction. The last stage Post-review involves introspection necessary for continuous quality improvement of lessons. The validity of the instruction consulting elements for Flipped Learning applied to deduce the aforementioned results has been verified after specialist review and field application.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.103-104
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• 2006

The following instruction gives you a guideline the method of application for ABS, Ergonomics design

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.71-80
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• 2004

In this paper, we study for the design and verification of a 16 bits micro controller, which is compatible with a 8 bits micro controller, 8051, widely used in the industrial fields these days. To confirm our design, we verified our design for all instruction sets and various combinational sets of them. Also we propose a new idea for the verification of various instruction sets, We verified our design through some application programs such as IMA-ADPCM, SOLA. Finally, we verified our design for all instruction sets and application programs through an application board, used Xilinx FPGA(XCVl000-560C). After the comparison our design with a 8051 for various cases, We concluded that we could substitute our design for a 8051 and our design could be operated more powerfully than a 8051.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.1-4
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• 2014

Although physical modeling synthesis is becoming more and more efficient in rich and natural high-quality sound synthesis, its high computational complexity limits its use in portable devices. This constraint motivated research of single-instruction multiple-data many-core architectures that support the tremendous amount of computations by exploiting massive parallelism inherent in physical modeling synthesis. Since no general consensus has been reached which grain sizes of many-core processors and memories provide the most efficient operation for sound synthesis, design space exploration is conducted for seven processing element (PE) configurations. To find an optimal PE configuration, each PE configuration is evaluated in terms of execution time, area and energy efficiencies. Experimental results show that all PE configurations are satisfied with the system requirements to be implemented in portable devices.