• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.6
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• pp.1049-1057
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• 2011

Today, most weapon systems operate as component systems of SoS(System of Systems) and they produce synergy effects in the battle field by interoperating. In addition, the acquisition issues on weapon systems have expanded into SoS context including sustainment analysis. Availability is the sustainment KPP(Key Performance Parameter) of weapon systems. In this paper, a simulation model is proposed to analyze the availability of SoS. The simulation model consists of 5 modules: Mission and Task, System, System RBD, Maintenance system and a simulation engine. Then it was implemented and applied to a SoS. As a result of the application, the simulation model could be applied for analyzing the availability of the SoS and provided information about critical tasks and risky component systems to complete the given mission of the SoS.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2011.04a
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• pp.367-370
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• 2011

A high-resolution numerical study is carried out to investigate the transient process of the combustion and the shock-train developments in an ethylene-fueled direct-connect dual-mode scramjet combustor. Air-throttling is then applied at the expansion part of the combustor to provide mass addition to block the flow to subsonic speed, hence to enhance the fuel-air mixing and ignition. Present simulation shows the detailed results for the better understanding of transient processes of the operation regimes in the dual-mode scramjet combustor.

• Journal of information and communication convergence engineering
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• v.16 no.4
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• pp.258-263
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• 2018

Color Doppler sonography is a useful tool for examining blood flow and related indices. However, it should be done by well-trained operator, that is, operator subjectivity exists. In this paper, we propose an automatic blood flow area extraction method from brachial artery that would be an essential building block of computer aided color Doppler analyzer. Specifically, our concern is to examine hypertension suspicious (prehypertension) patients who might develop their symptoms to established hypertension in the future. The proposed method uses fuzzy C-means clustering as quantization engine with careful seeding of the number of clusters from histogram analysis. The experiment verifies that the proposed method is feasible in that the successful extraction rates are 96% (successful in 48 out of 50 test cases) and demonstrated better performance than K-means based method in specificity and sensitivity analysis but the proposed method should be further refined as the retrospective analysis pointed out.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.15 no.2
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• pp.95-100
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• 1979

In fishing with the anchovy boat seine, it is required to haul up the bag net without injuring anchovy body. Not to injure anchovy body, the bag net is operated with 30 to 34 crews in the traditional method. With a view point of decreasing crews, the authors tried to operate the bag net with side drum winch and derrick boom. Side drum winch was installed beside the engine casing and it was operated by the main engine through the belt, pulley and bevel gear. The derrick boom, 7 meters long, was installed above the working deck which is located in the stern of the common boat seiner. Three single blocks are attached to the boom, each 2 meters apart from the top. A hook was attached to the free end of the block line for hooking up the bolch line which attached inside the bag net especially prepared for the purpose. The hauling end of the block line was induced to the side drum winch for hauling up the bag net. By using this mechanism, the bag net was hauled up with peeling the bag net just like in the traditional method. So the following results are found. (1) No injury of anchovy body was found in the process of hauling up. (2) The bag net can be operated by mere 14 crews. (3) Duration, spent in hauling up the bag net, was almost the same when the catch are a little amount, and less duration was needed by the experimented method than the traditional one when the catch are a large amount. the bag net. By using this mechanism, the bag net was hauled up with peeling the bag net just like in the traditional method. So the following results are found. (1) No injury of anchovy body was found in the process of hauling up. (2) The bag net can be operated by mere 14 crews. (3) Duration, spent in hauling up the bag net, was almost the same when the catch are a little amount, and less duration was needed by the experimented method than the traditional one when the catch are a large amount.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.5
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• pp.1008-1013
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• 2009

In this paper, we proposed the biological signal (body heat, pulse, breathe rate, and blood pressure) analysis system using wireless sensor. In order to analyze, we designed a back-propagation neural network system using expert group system. The proposed system is consist of hardware patt such as UStar-2400 ISP and Wireless sensor and software part such as Knowledge Base module, Inference Engine module and User Interface module which is inserted in Host PC. To improve the accuracy of the system, we implement a FEC (Forward Error Correction) block. For conducting simulation, we chose 100 data sets from Knowledge Base module to train the neural network. As a result, we obtained about 95% accuracy using 128 data sets from Knowledge Base module and acquired about 85% accuracy which experiments 13 students using wireless sensor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.28-34
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• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1985-1992
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• 2011

PE(Passive Entry) is an automotive technology which allows a driver to lock and unlock door of vehicle without using smart key buttons personally. PG(Pssive Go) is an automotive technology which offers the ability to start and stop the engine when there is a driver in vehicle with smart key. When these two functions are unified, we call it PEG(Passive Entry/Go). LF(Low Frequency) antenna driver which is one of core technologies in PEG is composed of a digital part which processes commands and an analog part which generates sine waveform. The digital part of antenna driver receives commands from MCU(or ECU), and processes requested commands by MCU, and stores antenna-related driver commands and data on an internal FIFO block. The digital part takes corresponding actions for commands read from FIFO and then transfers modulated LF data to analog part. The analog part generates sine waveform and transmits outside through antenna. The designed digital part for LF antenna driver can acomplish faster LF data transmission than that of conventional product. LF antenna driver can be applicable to the areas such as PEG for automotive and gate opening and closing of building.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.329-334
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• 2014

This paper proposes the hardware architecture of high performance multi-mode 2D forward transform for HEVC which has same number of cycles for processing any type of four TUs and yield high throughput. In order to make the original image which has high pixel and high resolution into highly compressed image effectively, the transform technique of HEVC supports 4 kinds of pixel units, TUs and it finds the optimal mode after performs each transform computation. As the proposed transform engine uses the common computation operator which is produced by analyzing the relationship among transform matrix coefficients, it can process every 4 kinds of TU mode matrix operation with 35cycles equally. The proposed transform block was designed by Verilog HDL and synthesized by using TSMC 0.18um CMOS processing technology. From the results of logic synthesis, the maximum operating frequency was 400MHz and total gate count was 214k gates which has the throughput of 10-Gpels/cycle with the $4k(3840{\times}2160)@30fps$ image.