• 제목/요약/키워드: Encryption Performance

검색결과 418건 처리시간 0.025초

안전한 MQTT 통신을 위한 경량 암호화 방법에 관한 연구 (A Study on the Lightweight Encryption Method for Secure MQTT Communication)

  • 전유란;주소영;이일구
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2022년도 춘계학술대회
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    • pp.82-84
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    • 2022
  • 최근 IoT(Internet of Things) 기기의 수가 증가함에 따라 발생하는 오버헤드 문제를 해결하기 위한 연구가 활발히 진행되고 있다. IoT 환경에서의 성능저하 문제를 해결하기 위한 IoT 경량화 프로토콜 중 하나인 MQTT(Message Queue Telemetry Transport)는 다대다 통신 환경에서 효율적인 동작이 가능하도록 표준화되었지만, 통신 시스템에 적용되어 구현될 때 암호화를 하지 않는 것이 디폴트로 설정되어 보안이 취약한 문제가 있다. 이러한 문제를 해결하기 위해 TLS(Transport Layer Security) 암호화 통신 기술을 적용할 수 있지만, IoT의 경량 저전력 요구조건을 만족하기 어렵다. 본 논문에서는 최신 MQTT 통신 암호화 기술 동향을 소개하고, TLS 암호화 통신 및 페이로드 암호화 방식을 비교하여 IoT 적용 가능성을 분석한다.

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3중 DES와 DES 암호 알고리즘용 암호 프로세서와 VLSI 설계 (VLSI Design of Cryptographic Processor for Triple DES and DES Encryption Algorithm)

  • 정진욱;최병윤
    • 한국멀티미디어학회:학술대회논문집
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    • 한국멀티미디어학회 2000년도 춘계학술발표논문집
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    • pp.117-120
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    • 2000
  • This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

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블록 암호 ARIA를 위한 고속 암호기/복호기 설계 (Design of High Speed Encryption/Decryption Hardware for Block Cipher ARIA)

  • 하성주;이종호
    • 전기학회논문지
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    • 제57권9호
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    • pp.1652-1659
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    • 2008
  • With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

Reverse Iterative Image Encryption Scheme Using 8-layer Cellular Automata

  • Zhang, Xing;Zhang, Hong;Xu, Chungen
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제10권7호
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    • pp.3397-3413
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    • 2016
  • Considering that the layered cellular automata (LCA) are naturally fit for representing image data in various applications, a novel reverse iterative image encryption scheme based on LCA is proposed. Specifically, the plain image is set as the final configuration of an 8-layer CA, and some sequences derived from a random sequence are set as the pre-final configuration, which ensure that the same plain image will never be encrypted in the same way when encrypted many times. Then, this LCA is backward evolved by following some reversible two order rules, which are generated with the aid of a newly defined T-shaped neighborhood. The cipher image is obtained from the recovered initial configuration. Several analyses and experimental results show that the proposed scheme possesses a high security level and executive performance.

HIGHT 암복호화 병렬 실행을 위한 Key Scheduler 설계 (Design of a Key Scheduler for Supporting the Parallel Encryption and Decryption Processes of HIGHT)

  • 최원정;이제훈
    • 센서학회지
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    • 제24권2호
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    • pp.107-112
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    • 2015
  • HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

부분 암호화를 위한 해쉬 트리 체인 기반 키 생성 및 관리 알고리즘 (Key Generation and Management Scheme for Partial Encryption Based on Hash Tree Chain)

  • 김경민;손규식;남승엽
    • 한국시뮬레이션학회논문지
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    • 제25권3호
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    • pp.77-83
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    • 2016
  • 본 논문에서는 부분 암호화를 위한 키 생성 및 관리 알고리즘의 연구한다. 제안하는 알고리즘에서는 해쉬 트리 구조를 이용하여 적은 양의 해쉬키로부터 다양한 암호화 키를 생성하는 기능을 제공하고 있다. 본 논문에서는 새로운 키 생성 알고리즘을 이용하여 부분 암호화 및 부분 복호화하는 방법을 제시하고 시뮬레이션을 통하여 그 성능을 분석한다.

Secure Outsourced Computation of Multiple Matrix Multiplication Based on Fully Homomorphic Encryption

  • Wang, Shufang;Huang, Hai
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제13권11호
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    • pp.5616-5630
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    • 2019
  • Fully homomorphic encryption allows a third-party to perform arbitrary computation over encrypted data and is especially suitable for secure outsourced computation. This paper investigates secure outsourced computation of multiple matrix multiplication based on fully homomorphic encryption. Our work significantly improves the latest Mishra et al.'s work. We improve Mishra et al.'s matrix encoding method by introducing a column-order matrix encoding method which requires smaller parameter. This enables us to develop a binary multiplication method for multiple matrix multiplication, which multiplies pairwise two adjacent matrices in the tree structure instead of Mishra et al.'s sequential matrix multiplication from left to right. The binary multiplication method results in a logarithmic-depth circuit, thus is much more efficient than the sequential matrix multiplication method with linear-depth circuit. Experimental results show that for the product of ten 32×32 (64×64) square matrices our method takes only several thousand seconds while Mishra et al.'s method will take about tens of thousands of years which is astonishingly impractical. In addition, we further generalize our result from square matrix to non-square matrix. Experimental results show that the binary multiplication method and the classical dynamic programming method have a similar performance for ten non-square matrices multiplication.

클라우드와 포그 컴퓨팅 기반 IoT 서비스를 위한 보안 프레임워크 연구 (A Study on the Security Framework for IoT Services based on Cloud and Fog Computing)

  • 신민정;김성운
    • 한국멀티미디어학회논문지
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    • 제20권12호
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    • pp.1928-1939
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    • 2017
  • Fog computing is another paradigm of the cloud computing, which extends the ubiquitous services to applications on many connected devices in the IoT (Internet of Things). In general, if we access a lot of IoT devices with existing cloud, we waste a huge amount of bandwidth and work efficiency becomes low. So we apply the paradigm called fog between IoT devices and cloud. The network architecture based on cloud and fog computing discloses the security and privacy issues according to mixed paradigm. There are so many security issues in many aspects. Moreover many IoT devices are connected at fog and they generate much data, therefore light and efficient security mechanism is needed. For example, with inappropriate encryption or authentication algorithm, it causes a huge bandwidth loss. In this paper, we consider issues related with data encryption and authentication mechanism in the network architecture for cloud and fog-based M2M (Machine to Machine) IoT services. This includes trusted encryption and authentication algorithm, and key generation method. The contribution of this paper is to provide efficient security mechanisms for the proposed service architecture. We implemented the envisaged conceptual security check mechanisms and verified their performance.

USN 화재방재 시스템을 위한 보안 통신 구현 및 실험 (Security Communication Implementation and Experiments for USN Fire Prevention System)

  • 김영혁;임일권;이재광
    • 컴퓨터교육학회논문지
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    • 제13권6호
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    • pp.99-104
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    • 2010
  • USN 화재방재 시스템은 온도, 습도, 조도, 가속도, CO2 등의 다양한 센서로부터 얻는 데이터를 이용해 관리자에게 전달하고, 화재를 판별하는 화재 판별 알고리즘을 이용하여 소화설비를 동작시키는 지능적인 시스템이다. USN 화재방재 시스템은 센서의 데이터에 전적으로 의지하여 동작함으로 본 논문에서는 분산된 각각의 센서 데이터들을 임베디드 시스템 환경에서 효율적이고 안전하게 수집, 전달하기 위한 모델을 제안한다. 패킷의 구성과 패키징은 저 전력 소모를 위해 최대한 가볍고 빠른 처리 과정을 거치게 설계하였으며, 현재 나와 있는 암호화 알고리즘 중 DES, 3DES, AES, HIGHT를 각각 적용, 빠른 암복호화에 목표를 두어 최종적으로 국내에서 제안한 표준 암호화 알고리즘인 HIGHT가 잦은 센싱 시간을 요구하는 화재방재 시스템에 적합함을 확인하였다.

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OpenSSL 상에서 LEA 설계 및 구현 (Design and Implementation of Lightweight Encryption Algorithm on OpenSSL)

  • 박기태;한효준;이재훈
    • 한국통신학회논문지
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    • 제39B권12호
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    • pp.822-830
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    • 2014
  • 최근 인터넷 환경에서 보안 서비스가 중요시 되면서 SSL/TLS의 사용은 행정기관뿐만 아니라 개인 홈페이지에서도 증가되고 있는 추세이다. 또한 IETF는 사물인터넷 환경에서도 제한된 성능과 자원을 가진 디바이스들이 보안기능을 위해 사용할 수 있도록 DTLS의 적용을 제안하고 있다. 본 논문에서는 LEA알고리즘을 구현하고 이를 OpenSSL 상에 적용 하였다. 그 결과 구현된 알고리즘은 AES 등과 같은 다른 대칭키 알고리즘들과 비교했을 때 연산 속도에 있어 우수한 성능을 보임을 확인 하였다.