• Title/Summary/Keyword: Emitter etch-back

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Contact Resistance Analysis of High-Sheet-Resistance-Emitter Silicon Solar Cells (고면저항 에미터 결정질 실리콘 태양전지의 전면전극 접촉저항 분석)

  • Ahn, Jun-Yong;Cheong, Ju-Hwa;Do, Young-Gu;Kim, Min-Seo;Jeong, Ji-Weon
    • New & Renewable Energy
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    • v.4 no.2
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    • pp.74-80
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    • 2008
  • To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

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CONTACT RESISTANCE ANALYSIS OF HIGH-SHEET-RESISTANCE-EMITTER SILICON SOLAR CELLS (고면저항 에미터 결정질 실리콘 태양전지의 전면전극 접촉저항 분석)

  • Ahn, Jun-Yong;Cheong, Ju-Hwa;Do, Young-Gu;Kim, Min-Seo;Jeong, Ji-Weon
    • 한국신재생에너지학회:학술대회논문집
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    • 2008.05a
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    • pp.390-393
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    • 2008
  • To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

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Effects of Laser Doping on Selective Emitter Si Solar Cells (레이져를 이용한 도핑 특성과 선택적 도핑 에미터 실리콘 태양전지의 제작)

  • Park, Sungeun;Park, Hyomin;Nam, Junggyu;Yang, JungYup;Lee, Dongho;Min, Byoung Koun;Kim, Kyung Nam;Park, Se Jin;Lee, Hae-Seok;Kim, Donghwan;Kang, Yoonmook;Kim, Dongseop
    • Current Photovoltaic Research
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    • v.4 no.2
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    • pp.54-58
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    • 2016
  • Laser-doped selective emitter process requires dopant source deposition, spin-on-glass, and is able to form selective emitter through SiNx layer by laser irradiation on desired locations. However, after laser doping process, the remaining dopant layer needs to be washed out. Laser-induced melting of pre-deposited impurity doping is a precise selective doping method minimizing addition of process steps. In this study, we introduce a novel scheme for fabricating highly efficient selective emitter solar cell by laser doping. During this process, laser induced damage induces front contact destabilization due to the hindrance of silver nucleation even though laser doping has a potential of commercialization with simple process concept. When the laser induced damage is effectively removed using solution etch back process, the disadvantage of laser doping was effectively removed. The devices fabricated using laser doping scheme power conversion efficiency was significantly improved about 1% abs. after removal the laser damages.

Fabrication and characterization of silicon field emitter array with double gate dielectric (이중 게이트 절연막을 가지는 실리콘 전계방출 어레이 제작 및 특성)

  • 이진호;강성원;송윤호;박종문;조경의;이상윤;유형준
    • Journal of the Korean Vacuum Society
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    • v.6 no.2
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    • pp.103-108
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    • 1997
  • Silicon field emitter arrays (FEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and $O_2$ plasma ashing on order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The hight and the end radius of the fabricated emitter was about 1.1 $\mu\textrm{m}$ and less than 100$\AA$, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

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A study of etch-back structure for high efficiency in crystalline silicon solar cells (결정질 태양전지의 고효율화를 위한 선택적 도핑 중 에치-백 구조에 관한 연구)

  • Jung, Woo-Won;Yang, Du-Hwan;Lee, Yong-U;Gong, Dae-Yeong;Kim, Seon-Yong;Yi, Jun-Sin
    • 한국신재생에너지학회:학술대회논문집
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    • 2009.11a
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    • pp.347-347
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    • 2009
  • 결정질 태양전지의 공정에 있어서 호모지니어스(homogeneous)한 구조보다 향상된 변환효율을 얻기 위해 선택적 도핑 방법에 관한 연구가 활발하다. 선택적 도핑 방법이란 에미터(emitter) 층을 $n^{++}$ 영역과 $n^+$ 영역으로 나누어 향상된 전류밀도와 개방전압을 얻기 위한 방법이다. 본 연구에서 제시된 RIE 에치-백 구조는 다수의 선택적 도핑 방법 중 하나이다. 기존의 에치-백 구조는 전면 전극 형성 후 RIE 공정을 수행하기 때문에 전면 전극이 손상되고 RIE 데미지(damage)가 발생되는 문제점이 있었다. 그러나 본 연구에서 제시된 구조는 기존의 에치-백 구조와 달리 RIE 에칭 후 발생된 데미지를 제거하는 추가적인 공정인 질산 패시베이션(nitric acid passivation)이 수행되었다. 또한 본 연구에서 새롭게 제시된 블라킹 마스크 페이스트(blocking mask paste)는 기존의 에치-백 구조에서 발생된 전극 손상 문제를 해결해 주고 있다. 이러한 결과로 호모지니어스 구조보다 향상된 전류밀도 (35.77 mA/$cm^2$), 개방전압 (625 mV), FF (78.01%), 변환효율 (17.43%)를 얻었다.

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Crystalline Silicon Solar Cell with Selective Emitter Using One-step Diffusion Process (One-step diffusion으로 형성된 선택적 에미터 결정질 실리콘 태양전지에 관한 연구)

  • Jeong, Kyeong-Taek;Yang, O-Bong;Yu, Gwon-Jong;Lee, Jeong-Chul;Song, Hee-Eun
    • 한국태양에너지학회:학술대회논문집
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    • 2011.11a
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    • pp.40-44
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    • 2011
  • Recent studies in crystalline silicon solar cell fabrication have been focused on high efficiency and low cost. However, the rising of the cost results in additional processes to approach high efficiency. The fabrication process also becomes complicated with additional technologies. In this paper, we studied the selective emitter formation with phosphorous paste to improve the conversion efficiency. Selective emitter formations like two-step diffusion or etch-back method require at least one more step compared in the conventional line since heavily and lightly doped area was needed to form separately.However,one-step diffusion process is the method diffusing heavily and lightly doped area at the same time only with additional screen-printing step. This study lays the foundation for the simple way to form the selective emitter.

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Fabrication of Double Textured Selective Emitter Si Solar Cell Usning Electroless Etching Process (이중 텍스쳐 구조를 적용한 선택적 에미터 태양전지의 특성 분석)

  • Kim, Changheon;Lee, Jonghwan;Lim, Sangwoo;Jeong, Chaehwan
    • Current Photovoltaic Research
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    • v.2 no.3
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    • pp.130-134
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    • 2014
  • We have fabricated the selective emitter solar cell using double textured nanowires structure. The $40{\times}40mm2$-sized silicon substrates were textured to form the pyramid-shaped surface and the nanowires were fabricated by metal assisted chemical etching process using Ag nanoparticles, subsequently. The heavily doped and shallow emitters for selectiv eemitter solar cells were prepared through the thermal $POCl_3$ diffusion and chemical etch-back process, respectively. The front and rear electrodes were prepared following conventional screen printing method and the widths of fingers have been optimized. The selective emitter solar cell using double textured nanowires structure achieved a conversion efficiency of 17.9% with improved absorption and short circuit current density.

Fabrication and Operating Properties of Nb Silicide-coated Si-tip Field Emitter Arrays (니오비움 실리사이드가 코팅된 실리콘 팁 전계 방출 소자의 제조 및 동작 특성)

  • Ju, Byeong-Kwon;Park, Jae-Seok;Lee, Sangjo;Kim, Hoon;Lee, Yun-Hi;Oh, Myung-Hwan
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.7
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    • pp.521-524
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    • 1999
  • Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

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Active-Matrix Field Emission Display with Amorphous Silicon Thin-Film Transistors and Mo-Tip Field Emitter Arrays

  • Song, Yoon-Ho;Hwang, Chi-Sun;Cho, Young-Rae;Kim, Bong-Chul;Ahn, Seong-Deok;Chung, Choong-Heui;Kim, Do-Hyung;Uhm, Hyun-Seok;Lee, Jin-Ho;Cho, Kyoung-Ik
    • ETRI Journal
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    • v.24 no.4
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    • pp.290-298
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    • 2002
  • We present, for the first time, a prototype active-matrix field emission display (AMFED) in which an amorphous silicon thin-film transistor (a-Si TFT) and a molybdenum-tip field emitter array (Mo-tip FEA) were monolithically integrated on a glass substrate for a novel active-matrix cathode (AMC) plate. The fabricated AMFED showed good display images with a low-voltage scan and data signals irrespective of a high voltage for field emissions. We introduced a light shield layer of metal into our AMC to reduce the photo leakage and back channel currents of the a-Si TFT. We designed the light shield to act as a focusing grid to focus emitted electron beams from the AMC onto the corresponding anode pixel. The thin film depositions in the a-Si TFTs were performed at a high temperature of above 360°C to guarantee the vacuum packaging of the AMC and anode plates. We also developed a novel wet etching process for $n^+-doped$ a-Si etching with high etch selectivity to intrinsic a-Si and used it in the fabrication of an inverted stagger TFT with a very thin active layer. The developed a-Si TFTs performed well enough to be used as control devices for AMCs. The gate bias of the a-Si TFTs well controlled the field emission currents of the AMC plates. The AMFED with these AMC plates showed low-voltage matrix addressing, good stability and reliability of field emission, and good light emissions from the anode plate with phosphors.

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Fabrication of New Co-Silicided Si Field Emitter Array with Long Term Stability (Co-실리사이드를 이용한 새로운 고내구성 실리콘 전계방출소자의 제작)

  • Chang, Gee-Keun;Kim, Min-Young;Jeong, Jin-Cheol
    • Korean Journal of Materials Research
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    • v.10 no.4
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    • pp.301-304
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    • 2000
  • A new triode type Co-silicided Si FEA(field emitter array) was realized by Co-silicidation of Co coated Si FEA and its field emission properties were investigated. The field emission properties of the fabricated device through the unit pixel with $45{\times}45$ tip array in the area of $250{\mu\textrm{m}}{\times}250{\mu\textrm{m}}$ under high vacuum condition of $10^{-8}Torr$ were as follows : the turn-on voltage was about 35V and the anode current was about $1.2\mu\textrm{A}(0.6㎁/tip)$ at the bias of $V_A=500V\;and\; V_G=55V$. The fabricated device showed the stable electrical characteristics without degradation of field emission current for the long term operation except for the initial transient state. The low turn-on voltage and the high current stability of the Co-silicided Si FEA were due to the thermal and chemical stability and the low work function of silicide layer formed at the surface of Si tip.

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