• Journal of Information Processing Systems
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• v.3 no.1
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• pp.16-20
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• 2007

This paper describes the development of the sensor interface and driver program for a point of care (POC) device. The proposed pac device comprises an ARM9 embedded processor and eight-channel sensor input to measure various bio-signals. It features a user-friendly interface using a full-color TFT-LCD and touch-screen, and a bluetooth wireless communication module. The proposed device is based on the system on a programmable chip (SOPC). We use Altera's Excalibur device, which has an ARM9 and FPGA area on a chip, as a test bed for the development of interface hardware and driver software.

• Journal of the Korea Society of Computer and Information
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• v.14 no.10
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• pp.23-29
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• 2009

This paper presents the development of embedded network educational system. This is an educational equipment which enables user to have training over Network Configuration and Embedded network programming practice on Internet environment. The network education system is developed on embedded environment. based on using ethernet interface. On the development environment. PAX255 VLSI chip is used for the processor, the ADSv1.2 for debugging, uC/OS276 for RTOS. The system software was developed using C language. The ping program provided an educational environment for the student to compile and load it to run after doing practice of demonstration behavior. Afterwards programming procedure starts the step-by-step training just like the demonstration function. In other words, programming method how to design the procedure of ARP operation and ICMP operation is explained.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.551-554
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• 2008

Do subject addition of existent picture reflex inside in this treatise as system that confirmation is available, do subject addition of picture reflex inside through GPS's photography position and Come on! direction angle of deviation campus to do confirmation possibility system design. Constructed each environment of Windows Operating System and embedded system environment for verification of system that is subject position of designed picture reflex also. To development environment of embedded system S3C2440A & used PXA270 processor, Camera and GPS in development baud, Come on! include deviation campus, and development language embodied in C language, and debugging environment did debugging using GCC compiler of Linux environment. PC software for verification designed system to confirm for subject position confirmation of picture reflex through Almap, Google Eartch developed verification software using visual C++. Also, groped way to utilize picture file by various field including position information within picture. Confirmed that decreased by error extent 1m within of radius 10m that is existent GPS's error extent as verification result.

• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.1
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• pp.160-165
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• 2003

The design and implementation of an engine control system has become an important area in developing a new car, but the implementation of an engine control system is becoming a tedious and time-consuming work as the level of complexity increases. In order to shorten the development cycle of the control system, rapid control prototyping (RCP) technique deserves developers' attention. A new RCP platform has been developed for an automotive engine control application. This prototyping system strictly adheres to the layered architecture of the final production ECU, and separates the automatically generated part of software, or the application area, from the hand coded area, which generally carefully designed and tested because of the hardware dependency and the efficiency of microcontroller. The $Matlab{\circledR}$ tool-chain of Mathworks Inc. has been selected as a base environment in this study. A newly developed Engine Control Toolbox of Real-Time $Workshop{\circledR}$ converts a graphically represented control algorithm into optimized application codes and links them with other parts of the software to generate executable code for the target processor.

• The Journal of the Korea Contents Association
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• v.12 no.6
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• pp.68-77
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• 2012

As the system development environment moves from single core to multi core-based platforms, it becomes more important to maintain compatibility between single core-based implementations and multi core-based implementations. Moreover, it is very important to support real-time on multi core platforms especially in cases of embedded software or test equipments which need real-time as well as correctness. Since Windows operating system dopes not support real-time in itself, it has been supporting real-time using expensive third-party solutions such as RTX or INtime. So as to reduce this kind of development expenses, in this paper, we propose RTiK-MP(Real-Time implant Kernel-Multi Processor) which supports real-time on Windows using the Local APIC of x86 architectures, and evaluate the performance of the proposed RTiK-MP after deploying it on portable missile test equipments.

• The Journal of Information Technology
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• v.6 no.3
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• pp.65-73
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• 2003

The evaluation AP embedded Linux board is implemented. The board is made of IBM 405 GP processor, PPCBoot-1.2.1 boot loader, Linux-2.4.21 kernel and root file system. The evaluation board has two flash memories, boot flash and application flash of size 512Kbyte and 16Mbyte, respectively. And it supports IEEE 802.11a which provide the maximum throughput of 54Mbps in the 5.2GHz frequency band. MTD(Memory Technology Device) and JFFS2(Journalling Flash File System version 2) technologies are adopted to optimally package the system software, boot loader, kernel and root file system. And in order to optimize root file system, busybox package and tiny login are used. Linux kernel and root file system is combined together with mkimage utility.

• Smart Media Journal
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• v.3 no.4
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• pp.9-15
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• 2014

A virtual platform models a processor core and the peripheral devices constituting the SoC in software. Major companies utilize a variety of platforms for product development with optimal SW+SoC integrated system architecture design and IP reuse based Top-Down design flow using a virtual platform. In this paper, we propose a virtual platform based on OpenRISC, an open source RISC based core. The proposed virtual platform supports high speed emulation of approximately 20 MIPS using DBT (Dynamic Binary Translation).

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.76-84
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• 2009

This paper proposes a SOC platform which is eligible for education and application SOC design. The platform, fully synthesizable and reconfigurable, includes the OpenRISC embedded processor, some basic peripherals such as GPIO, UART, debug interlace, VGA controller and WISHBONE interconnect. The platform uses a set of development environment such as compiler, assembler, debugger and RTOS that is built for HW/SW system debugging and software development. Designed SOC, IPs and Testbenches are described in the Verilog HDL and verified using commercial logic simulator, GNU SW development tool kits and the FPGA. Finally, a multimedia SOC derived from the SOC platform is implemented to ASIC using the Magnachip cell library based on 0.18um 1-poly 6-metal technology.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.687-692
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• 2009

This paper presents the development of RFID educational system based on 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The ATmega128 VLSI chip is used for the processor of the reader and the active tag. As the development environment, AVR compiler is used for the reader and the active tag of which the programming language is C. The visual C++language of the visual studio on the PC activated as the server is used for development language. Main functions of this system are to control tag containing EPC global Data by PC through the reader, to obtain information of tag through the internet and to read/write data on tag memory. Software design of 900MHz RFID/USN educational system is done on the basis of these functions.