• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• The KIPS Transactions:PartD
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• v.15D no.3
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• pp.355-360
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• 2008

The complicated embedded system for multi-tasking requires RTOS(real-time operating system). It uses the optimal OS and processor to each embedded system on the heterogeneous development environment. This paper is proposed to use UML profile of OS API and Processor Configuration, instead of cross-compiling for developing the heterogeneous embedded system. This reduces the development time and cost through generating the automatic source code with the profile information of each embedded system. We generate and port the code after modeling the two heterogeneous real time operating systems (brickOS and uC/OS-II) and the processors (Hitachi H8 and Intel PXA255) with our proposed profile of the heterogeneous embedded system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.72-79
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• 2007

This paper is an embedded system using the X-Hyper Intel PXA255 ARM CPU that base of the Linux operation system. This system applies tag information reading through RFID leader to Library executive system and designed and embody RFID middleware. The RFID middleware is consisted of RFID module, ARM processor and RS-232 interface. The RFID module is used to be inputted user and books information and RS-232 interface pass information by RFID middleware. Also, This system is embodied by specific Library management system using embedded exclusive use ARM processor. In this paper introduces concept and action principle of RFID middleware and uses Qt/Embedded and embodied manless loaning and return system.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.245-255
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• 2009

Recently, embedded processor systems have been widely used in the field of information communication devices and increased its use range and influence. The embedded systems are offered variety of functions, and its operating systems have been developed to make them easy to repair and maintain. Especially embedded linux is very cheap and provide a lot of equipment drivers. Also we can set up our own system because the source code is opened. In this paper, we describe the implementation of Touch panel and TFT-LCD device driver that are widely used for multimedia application. We designed the system hardware by using Altera Nios II embedded system. And we implemented the device drivers of frame buffer, touch panel and i2s based on uClinux for multimedia application, and tested actual operations of the integrated system.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.691-698
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• 2006

TCP/IP Offload Engine (TOE) is a technology that processes TCP/IP on a network adapter instead of a host CPU to reduce protocol processing overhead from the host CPU. There have been some approaches to implementing TOE: software TOE based on an embedded processor; hardware TOE based on ASIC implementation; and hybrid TOE in which software and hardware functions are combined. In this paper, we designed software modules and hardware modules for a hybrid TOE on an FPGA that had two processor cores. Software modules are based on the embedded Linux. Hardware modules are for data transmission (TX) and reception (RX). One core controls the TX path and the other controls the RX path of the Linux. This TX/RX path separation mechanism can reduce task switching overheads between processes and overcome poor performance of single embedded processor. Hardware modules deal with creating headers for outgoing packets, processing headers of incoming packets, and fetching or storing data from or to the host memory by DMA. These can make it possible to improve the performance of data transmission and reception. We proved performance of the TOE with separated transmission and reception paths by performing experiments with a TOE network adapter that was equipped with the FPGA having processor cores.

• ETRI Journal
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• v.34 no.1
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• pp.44-54
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• 2012

Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

• 유공압시스템학회:학술대회논문집
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• 2010.06a
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• pp.56-61
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• 2010

Simulator is a development equipment which enables the ECU to operate in normal mode by simulating the interface signal between ECU and mechanical system electrically. Embedded simulator means simulation function is embedded in ECU firmware, hence the electrical signal interface is replaced by the substitution of information at system program level. This paper explains the development of embedded transmission simulator for the verification of TCU firmware function which covers shifting control and on-board diagnosis. The embedded simulation program is executed in TCU processor along with the TCU firmware and it provides TCU firmware with not only the speed information those are appropriate both in driving and shifting conditions, but also the fault detection signals. Experimental results show that the validity of embedded simulator and its usefulness to the TCU firmware development and verification.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.15-25
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• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.4
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• pp.315-324
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• 2005

VOD(video on demand) is a video service by users' order, that is, a video service on demand. That means the users can select and watch the video content that has been saved on sewer, out of broadcasting in the usual process like TV. At present the client of VOD system bases on PC. As the PC-based client uses the software MPEG decoder, the main processor specification has an effect on the capacity. Also people, who don't know how to use their PC, cannot be provided the VOD service. The purpose of this paper is to show the process of the development the VOD client system Into the embedded type with hardware MPEG-4 decoder. The main processor is the SC1200 of x86 Family in National Semiconductor with a built-in video processor and the memory is 128Mbyte SDRAM. Also, in order that the VOD service can be provided using the Internet, the Ethernet controller is included. As the hardware MPEG-4 decoder is used in the embedded VOD client system, which is developed, it can make the low capacity of the main processor. Therefore it is able to be developed as a low-price system. The embedded VOD client system is easy for anyone to control easily with the remote control and can be played through TV.