• Title/Summary/Keyword: Embedded Memory

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Current and Future Trends of Smart Card Technology (스마트카드형 교통 카드의 기술 및 미래 동향)

  • Lee, Jung-Joo;Shon, Jung-Chul;Yu, Sin-Cheol
    • Proceedings of the KSR Conference
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    • 2008.06a
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    • pp.535-544
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    • 2008
  • Unlike MS(Magnetic Stripe), SMART CARD is equipped with COS(Chip Operating System) consisting of the Microprocessor and Memory where information can be stored and processed, and there are two types of cards according to the contact mode; the contact type that passes through a gold plated area and the contactless one that goes through the radio-frequency using an antenna embedded in the plastic card. the contactless IC card used for the transportation card was first introduced into local area buses in Seoul, and expanded throughout the country so that it has removed the inconvenience such as possession of cash, fare payment and collection. Focusing on the Seoul metropolitan area in 2004, prepaid and pay later cards were adopted and have been used interchangeably between a bus and subway. The card terminal compatible between a bus and subway is Proximity Integrated Circuit Card(PICC) as international standards(1443 Type A,B), communicates in the 13.56MHz dynamic frequency modulation-demodulation system, and adopts the Multi Secure Application Module(SAM). In the second half of 2009, the system avaliable nationwide will be built when the payment SAM standard is implemented.

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Power Efficient Scan Order Conversion for JPEG-Embedded ISP (JPEG이 내장된 ISP를 위한 전력 효율적인 스캔 순서 변환)

  • Park, Hyun-Sang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.5
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    • pp.942-946
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    • 2009
  • A scan order converter has to be placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. Recently a hardware architecture has been proposed to implement a scan converter based on the single line memory. Since both read and write accesses happen at each cycle, however, the largest part of the entire power budget is occupied by the SRAM itself. In this paper, the data packing and unpacking procedure is inserted in the processing chain, such that the access frequency to the SRAM is reduced to 1/8 by adopting a packed larger data unit. The simulation results show that the resultant power consumption is reduced down to 16% for the SXGA resolution.

Some Issues of Information Storage Management for GIS Applications on Pocket PC and Windows CE 3.0

  • Duc Duong Anh;Anh Le Thuy;Hung Son Do Lenh
    • Proceedings of the IEEK Conference
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    • summer
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    • pp.405-409
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    • 2004
  • The Pocket PC has become more popular in market because of the advantages of its small size and convenience for regular customers. Pocket PC is a mobile device so that we can receive the benefits of shared data over a wireless network. Enabling us to transmit data to a central location, simply messaging from one point to the next, its ability to share information across a wireless platform is becoming central to our communication needs. However, using Windows CE - an embedded operating system, as well as being designed for mobile users, there are many limitations to memory and speed of arithmetic operations on Pocket PC. As a result, developers have to deal with many difficulties in managing information storage when developing applications, especially Geography Information System (GIS) applications. In this paper, we propose some efficient methods to store GIS data and to increase the speed of displaying maps in GIS applications developed on Pocket PC and Windows CE 3.0.

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A Design of Programmable Fragment Shader with Reduction of Memory Transfer Time (메모리 전송 효율을 개선한 programmable Fragment 쉐이더 설계)

  • Park, Tae-Ryoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.12
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    • pp.2675-2680
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    • 2010
  • Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

Numerical Simulation and Verification of Morphing Composite Structure with Embedded SMA Wire Actuators (형상기억합금 선이 삽입된 가변 복합재 패널의 해석 및 실험)

  • Kong, Jung-Pyo;Jung, Beom-Seok;Li, Ningxue;Ahn, Sung-Hoon;Cho, Maeng-Hyo
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 2010.04a
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    • pp.343-346
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    • 2010
  • 형상기억합금이 삽입된 복합체는 힌지나 추가적 작동기 없이 그 자체로서 지능 구조의 역할을 할 수 있어 많은 분야에서 활발히 연구되고 있다. 본 논문에서는 형상기억합금(Shape Memory Alloy) 선이 삽입된 $\cap$자형 복합재를 제안하고, 형상기억합금과 모재가 정해진 경우의 곡률 변화에 영향을 주는 주요 설계 변수를 복합재의 너비, 두께, 형상기억합금의 편심률을 설계변수로 가정하고 유한요소 해석과 패널 제작 및 실험을 통해 검증한다. 먼저 라고다스(Lagoudas)모델을 형상기억합금의 구성방정식으로 이용한 유한요소해석모델을 구성하여 수치해석을 수행하고, 11 종류의 형상기억합금 선이 삽입된 유리섬유강화복합재(Glass Fiber Reinforced Plastic) 패널을 제작하여 열하중에 따른 곡률변화를 관찰한다. 해석결과와 실험결과의 비교를 통해 해석모델의 타당성을 검증하며, 해석을 통해 각 설계 변수들의 곡률변화에 대한 영향을 파악한다.

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Shortest Path Calculation Using Parallel Processor System (병력구조 전산기를 이용한 최단 경로 계산)

  • 서창진;이장규
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.34 no.6
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    • pp.230-237
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    • 1985
  • Shortest path calculations for a large-scale network have to be performed using a decomposition techniqre, since the calculations require large memory size which increases by the square of the number of vertices in the network. Also, the calculation time increases by the cube of the number of vertices in the network. In the decomposition technique,the network is broken into a number of smaller size subnetworks for each of which shortest paths are computed. A union of the solutions provides the solution of the original network. In all of the decomposition algirithms developed up to now, boundary vertices which divide all the subnetworks have to be included in computing shortest paths for each subnetwork. In this paper, an improved algorithm is developed to reduce the number of boundary vertices to be engaged. In the algorithm, only those boundary vertices that are directly connected to the subnetwork are engaged. The algorithm is suitable for an application to real time computation using a parallel processor system which consists of a number of micro-computers or prcessors. The algorithm has been applied to a 39- vertex network and a 232-vertex network. The results show that it is efficient and has better performance than any other algorithms. A parallel processor system has been built employing an MZ-80 micro-computer and two Z-80 microprocessor kits. The former is used as a master processor and the latter as slave processors. The algorithm is embedded into the system and proven effective for real-time shortest path computations.

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Development of the Small Gas Boiler Controller Using Web Browser (Web browser를 이용한 가정용 가스보일러 제어기술 개발)

  • Shon, Su-Goog
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.18 no.6
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    • pp.213-219
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    • 2004
  • This paper describes the developmnet of a web-based boiler controller which can be in parallel operated with an existing boiler controller. The web-based boiler controller mainly consists of RTL8019AS NIC and TS80C32 microcontroller. In order to communicate over the Internet, we need to develop network driver, IP, TCP, UDP, ICMP, and HTTP. For a specific application like web-boiler controller, we have proposed a common global data buffer algorithm to minimize the RAM memory usage. Finally, the correctness and performance of the protocols are tested and verified using CommView and Dummynet. The development is satisfactorily operated only for few hundreds of bytes of RAM usage without sacrificing interoperability between hosts.

HW/SW co-design of H.264/AVC Decoder using ARM-Excalibur (ARM-Excalibur를 이용한 H.264/AVC 디코더의 HW/SW 병행 설계)

  • Jung, Jun-Mo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.7
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    • pp.1480-1483
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    • 2009
  • In this paper, the hardware(HW) and software(SW) co-design methodology of H.264/AVC decoder using ARM-Excalibur is proposed. The SoC consists of embedded processor, memory, peripheral device and logic circuits. Recently, the co-design method which designs simultaneously HW and SW part is a new paradigm in SoC design. Because the optimization for partitioning the SoC system is very difficult, the verification must be performed earlier in design flow. We designed the H.264 and AVC Decoder using co-design method. It is shown that, for the proposed co-design method, the performance improvements can be obtained.

Displacement-recovery-capacity of superelastic SMA fibers reinforced cementitious materials

  • Choi, Eunsoo;Mohammadzadeh, Behzad;Hwang, Jin-Ha;Lee, Jong-Han
    • Smart Structures and Systems
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    • v.24 no.2
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    • pp.157-171
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    • 2019
  • This study investigated the effects of the geometric parameters of superelastic shape memory alloy (SE SMA) fibers on the pullout displacement recovering and self-healing capacity of reinforced cementitious composites. Three diameters of 0.5, 0.7 and 1.0 mm and two different crimped lengths of 5.0 and 10.0 mm were considered. To provide best anchoring action and high bond between fiber and cement mortar, the fibers were crimped at the end to create spear-head shape. The single fiber cement-based specimens were manufactured with the cement mortar of a compressive strength of 84 MPa with the square shape at the top and a dog-bone shape at the bottom. The embedded length of each fiber was 15 mm. The pullout test was performed with displacement control to obtain monotonic or hysteretic behaviors. The results showed that pullout displacements were recovered after fibers slipped and stuck in the specimen. The specimens with fiber of larger diameter showed better displacement recovering capacity. The flag-shaped behavior was observed for all specimens, and those with fiber of 1.0 mm diameter showed the clearest one. It was observed that the length of fiber anchorage did not have a significant effect on the displacement recovery, pullout resistance and self-healing capacity.

A Study of Interactive Digital Signage System using Heterogeneous Device (이기종 디바이스를 이용한 인터렉티브 디지털 사이니지 시스템 연구)

  • Park, Dae Seung;Sung, Yeol Woo;Kim, Cheong Ghil
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.3
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    • pp.184-188
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    • 2021
  • In general, digital signage is a next-generation smart media that provides various information and advertisement services to many people indoors or outdoors using the Internet. Recently, digital signage is rapidly spreading in such a small indoor environment, that is, in an area closely related to daily life, for example, inside an elevator. However, in this kind of indoor environment where the stay time of persons is extremely limited, it would be not easy for them to keep advertisements in the user memory for a long time. In the digital signage display installed in an indoor environment, it is possible to think about the possibility for a function such as expanding the screen to a user's smartphone, which is now widely spread, to contain, store, and use the transmitted content. In this paper, we propose a method to extend the display of digital signage contents to personal smart phones with interaction function in such a limited environment. In order to make the system operation, the proposed system was verified by confirming the result of dual screen implementation in a smart phone through the prototype implementation of a digital signage system in an embedded Linux environment.