• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.41-50
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• 2009

The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. Many researchers are studying the YAFFS, NAND flash file system, which is widely used in the embedded device. However, the existing YAFFS has two problems. First, it takes long time to mount the YAFFS file system because it scans whole spare areas in all pages. Second, the cleaning policy of the YAFFS does not consider the wear-leveling so that it cannot guarantee the duration of data completely. In order to solve these problems, this paper proposes a new content-based YAFFS that consists of a mounting time reduction technique and a content-cleaning policy by using content-based block management. The proposed method only scans partial spare areas of some special pages and provides the block swapping which enables the wear-leveling of data blocks. We performed experiments to compare the performance of the proposed method with those of the JFFS2 system and YAFFS system. Experimental results show that the proposed method reduces the average mounting time by 82.2% comparing with JFFS2 and 42.9% comparing with YAFFS. Besides, it increases the life time of the flash memory by 35% comparing with the existing YAFFS whereas no overheat is added.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.462-465
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• 2011

A pulse oximeter is a device which provides non-invasive estimate of percentage oxygen saturation of haemoglobin (SpO2). Due to the limitations of resources of personal health devices (PHDs) including pulse oximeters, they generally transmit the estimated data to a remote monitoring server through a close manager (e.g. mobile device or PC). Therefore, communication protocols between PHDs and a manager is an important research topic in terms of interoperability. In this paper, we present design results of an SpO2 transmission agent based on the ISO/IEEE 11073 (X73) protocol. The protocol is an international standard for PHDs. The agent is an embedded program which generates X73 messages from the estimated pulse rates and SpO2, and transmits the messages to a close manager. The agent consists of a Session, Message and Memory Handler. The Session Handler manages a communication session with the manager, and the Message Handler generates and analyzes the exchanged messages according to the X73 protocol. The Memory Handler extracts pulse rates and SpO2s which are stored in a memory of the pulse oximeter. The SpO2 transmission agent allows pulse oximeters to communicate with managers based on x73 standard. Consequently, the interoperability between the pulse oximeters and the managers is guaranteed.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.871-873
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• 2005

최근 임베디스 시스템의 성능이 향상됨에 따라, 임베디드 시스템을 구성하는 CPU와 주변 장치들의 성능 격차를 해소하는 문제가 점차 중요해지고 있다. 그 중에서 시스템의 성능에 가장 큰 영향을 미치는 것이 CPU와 메모리간의 통신이다. 고성능 컴퓨터 시스템에서는 그동안 CPU와 메모리간의 성능 격차를 줄이기 위한 여러 가지 연구들이 활발하게 진행되었는데, 여러 가지 연구들 중에서 메모리를 압축하여 메모리의 기억공간을 효율적으로 확장하는 방법이 효과적으로 사용되고 있다. 임베디드 시스템에서도 이러한 기법을 적절하게 적용하면 메모리를 압축함으로써 동일 공간에 보다 많은 데이터를 저장할 수 있고, 버스를 이용하여 데이터를 전송할 때, 보다 많은 정보를 전송할 수 있게 된다. 또한, CPU와 메모리 간의 전송되는 정보의 크기를 줄일 수 있으므로 임베디드 시스템에서 전력소모의 대부분을 차지하고 있는 CPU와 메모리 간의 전력소모를 크게 줄일 수 있는 장점이 있다. 본 논문에서는 빈발 패턴 압축 기법을 적절하게 변형하여 임베디드 시스템을 위한 효율적인 메모리 압축 기법을 제시하고자 한다.

• Journal of KIISE:Computing Practices and Letters
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• v.12 no.2
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• pp.102-110
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• 2006

This paper explains the design and development of the stand-alone high sound quality Internet Radio system, which is aimed for a small embedded type audio device rather than a general PC type. This device is designed to work with an Internet connection. This kind of system is not standardized so far, and also the related algorithm is not open to the public. So it is necessary to analyze several receiving algorithms of current radio receivers, and develop our own hardware in order to overcome these obstacles, finally to get the high quality of sound radio. The main electronic components of this Internet Radio are TCP/IP interfaces, an audio MP3 decoder, an I/O interface, and a Flash Memory Card with advanced audio multicasting for the next-generation Internet Radio. Basic structures and implementation issues of the next-generation most-versatile digital music player, and Internet Radio receivers, are discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.7
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• pp.601-604
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• 2006

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for $100{\mu}S$, respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for $200{\mu}S$. On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.17 no.2
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• pp.109-117
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• 2018

The experimental results are presented of an autonomous flight algorithm of a foldable quadcopter with airdrop launching functions. A foldable wing structure enabled the quadcopter to be inserted into a rocket container with limited space. The foldable quadcopter was then separated from the rocket in the air. The flight pattern was tracked using a global positioning system (GPS) with various sensors, including an inertial measurement unit (IMU) module until a designated target position was reached. Extensive field tests were conducted through an international rocket competition, ARLISS 2017, which was held in Black Rock Desert, Nevada, USA. The flight trajectory record of the experiments is stored in electrically erasable programmable read-only memory (EEPROM) embedded in the main control unit. The flight record confirmed that the quadcopter successfully separated from the rocket, executed flight toward the target for a certain length of time, and stably landed on the ground.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.351-354
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• 2008

실시간 요건을 필요로 하는 임베디드 시스템의 경우 예측가능성(predictability)이 매우 중요하다. 그렇기 때문에 이러한 시스템들은 가상 메모리를 사용하지 않는 단순한 실시간 운영체제(RTOS) 를 사용하는 경우가 일반적이다. 하지만, 임베디드 시스템에 요구되는 기능 요건들이 복잡해짐에 따라 Linux와 같은 가상 메모리 기반의 범용 운영체제를 채택하는 경우가 늘고 있으며, 이런 경향은 앞으로 더욱 심해질 전망이다. 가상메모리 시스템은 필요한 메모리 사용량을 줄일 수 있을 뿐만 아니라 응용 프로그램 개발과 디버깅을 용이하게 하기 때문에 기존의 복잡하고 어려운 실시간 운영체제의 개발환경을 사용하는 경우에 비해 높은 개발 생산성을 기대할 수 있다. 하지만, 가상 메모리 시스템의 요구 페이징 기법은 시스템의 예측가능성을 떨어뜨리기 때문에 일반적으로 실시간 요건을 필요로 하는 시스템에 적용되지 못하고 있다. 본 논문은 요구 페이징 기법의 사용을 전제로 한 임베디드 시스템의 실시간 요건을 만족시키기 위한 페이지 교체 기법을 제안한다.