• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.3
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• pp.187-192
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• 2015

Detecting human in images is a challenging task owing to their variable appearance and the wide range of poses the they can adopt. The first need is a robust feature set that allows the human form to be discriminated cleanly, even in cluttered background under difficult illumination. A large number of vision application rely on matching keypoints across images. These days, the deployment of vision algorithms on smart phones and embedded device with low memory and computation complexity has even upped the ante: the goal is to make descriptors faster compute, more compact while remaining robust scale, rotation and noise. In this paper we focus on improving the speed of pedestrian(walking person) detection using Histogram of Oriented Gradient(HOG) descriptors provide excellent performance and tracking using kalman filter.

• IE interfaces
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• v.17 no.spc
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• pp.97-102
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• 2004

AGV flowpath layout design is one of the most important steps for efficient AGV systems design. Since it was formulated by Gaskins & Tanchoco (1987), a unidirectional AGV flowpath layout design problem has been tackled by many researchers. However, the solution methods were traded off between the solution quality and the computational time. In this paper, a tabu search technique is applied to obtain a good solution for a relatively large problem in reasonable computational time. Specifically, fast construction algorithm for feasible initial solutions, long-term memory structure and neighbor solutions generation are adapted to the problem characteristics and embedded in the tabu search algorithm. Also, sets of computational experiments show that the proposed tabu search algorithm outperforms to the Ko and Egbelu's algorithm (2003).

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.229-231
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• 2003

내장형 실시간 시스템에서는 메모리 관리시스템의 구현에 있어 메모리 단편화와 시간 결정성 (determinism)의 문제를 해결하기 위한 방법 중의 하나로 고정크기의 메모리를 할당하는 기법이 사용되어진다 내장형 자바가상기계에서도 객체를 관리하는 메모리 구조인 힙에 이를 적용하여 활용할 수 있으며 실제 구현으로는 simpleRTJ가 있다. 고정크기의 메모리 할당기법은 구현이 간단하기 때문에 시스템이 단순해지고 실행에서의 오버헤드도 작아지는 장점이 있다. 하지만 고정크기의 객체할당 방식은 가장 큰 객체의 크기를 이용하여 모든 객체를 할당하기 때문에 내부단편화를 발생시키는 단점이 있다. 본 논문에서는 내부 단편화를 최소화하면서 고정크기 할당기법의 장점을 최대한 이용할 수 있도록 하기 위해 다수의 고정크기를 이용하여 객체를 할당하는 기법에 관해 설명하며 관련 실험을 통해 내부단편화 문제를 얼마나 해결할 수 있는지에 관해 기술한다.

• Speech Sciences
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• v.14 no.4
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• pp.157-167
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• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.761-762
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• 2008

This paper presents a hardware accelerator for accelerating vector graphics applications based on the OpenVG standard. Since our design mainly targets embedded applications, we focus on efficient uses of limited resources, especially the memory bandwidth. The designed accelerator can process the images of $640{\times}240$ pixels with moderate complexity at the rate of 30 frames per second.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1308-1311
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• 2002

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in wireless multimedia applications. The discussion will focus on the architectural design techniques for implementing a high-performance video compression/decompression chip at low power architectures. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz for 128k∼144kbps. By introducing the efficiently optimized Frame Memory Interface architecture, low power motion estimation and embedded ARM microprocessor and AMBA interface, the proposed MPEG-4 video codec has low power consumption for wireless multimedia applications such as IMT-2000.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.241-244
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• 2003

Nowadays image processing is very useful for some field of traffic applications. The one reason is we can construct the system in a low price, the other is the improvement of hardware processing power, it can be more fast to processing the data. In this study, I propose the traffic monitoring system that implement on the embedded system environment. The whole system consists of two main part, one is host controller board, the other is image processing board. The part of host controller board take charge of control the total system, interface of external environment. and OSD(On screen display). The part of image processing board takes charge of image input and output using video encoder and decoder, image classification and memory control of using FPGA, control of mouse signal. And finally, fer stable operation of host controller board, uC/OS-II operating system is ported on the board.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1399-1404
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• 1990

There is an increasing need to apply artificial intelligence to the real application fields of industry. These include an intelligent process control, an expert machine and a diagnostic and/or maintenance machine. These applications are implemented in AI Languages. It is commonly recognized that AI Languages, such as Common Lisp or Prolog, require a workstation. This is mainly due to the fact that both languages need a large amount of memory space and disk storage space. Workstations are appropriate for a laboratory or office environment. However, they are too bulky to use in the real application fields of industry or business. Also users who apply artificial intelligence to these fields wish to have their own operating systems. We propose a new design method of an intelligent controller which is embedded within equipment and provides easy-to-use tools for artificial intelligence applications. In this paper we describe the new design method of a VMEbus based intelligent controller for artificial intelligence applications and a small operating system which supports Common Lisp and Prolog.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.5
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• pp.477-481
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• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.