• The Journal of Korea Robotics Society
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• v.17 no.2
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• pp.133-141
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• 2022

This paper introduces model compression algorithms which make a deep neural network smaller and faster for embedded systems. The model compression algorithms can be largely categorized into pruning, quantization and knowledge distillation. In this study, gradual pruning, quantization aware training, and knowledge distillation which learns the activation boundary in the hidden layer of the teacher neural network are integrated. As a large deep neural network is compressed and accelerated by these algorithms, embedded computing boards can run the deep neural network much faster with less memory usage while preserving the reasonable accuracy. To evaluate the performance of the compressed neural networks, we evaluate the size, latency and accuracy of the deep neural network, DenseNet201, for image classification with CIFAR-10 dataset on the NVIDIA Jetson Xavier.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.241-246
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• 2021

In this paper, we developed the evaluation system for the active noise control so that the algorithms can be easily evaluated in real-time on the system. We implemented the active noise controller based on a single-chip with only additional op-amps for signal conditioning because the TMS320C280049 MCU includes almost all necessary peripherals for the active noise controller. Due to the difficulty in testing algorithms on embedded-type hardware unlike in computer simulation, we also developed GUI-based evaluation software which makes it simple to test algorithms on the hardware. Using the GUI software, we can optimize the parameters of the algorithms with ease in a specific noise environment because the parameters can be adjusted in real-time when the algorithm is running on the hardware.

• ETRI Journal
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• v.31 no.6
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• pp.732-740
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• 2009

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 ${\mu}m$ CMOS process and evaluated successfully on a real-time test board.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.89-93
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• 2009

Embedded systems are becoming more popular as many embedded platforms have become more affordable. It offers a compact solution for many different problems including computer vision applications. Texture classification can be used to solve various problems, and implementing it in embedded platforms will help in deploying these applications into the market. This paper proposes to deploy the texture classification algorithms onto the embedded computer vision (ECV) platform. Two algorithms are compared; grey level co-occurrence matrices (GLCM) and Gabor filters. Experimental results show that raw GLCM on MATLAB could achieves 50ms, being the fastest algorithm on the PC platform. Classification speed achieved on PC and ECV platform, in C, is 43ms and 3708ms respectively. Raw GLCM could achieve only 90.86% accuracy compared to the combination feature (GLCM and Gabor filters) at 91.06% accuracy. Overall, evaluating all results in terms of classification speed and accuracy, raw GLCM is more suitable to be implemented onto the ECV platform.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.77-78
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• 2010

As the maximum power operating point(MPOP) of photovoltaic(PV) power systems alters with changing atmospheric conditions, the efficiency of maximum power point tracking(MPPT) is important in PV power systems. Moreover, grid-connected PV system occurs some problems such as voltage inequality and harmonics. Therefore, this paper presents the results of a grid-connected PV system modeling by PSIM simulator and investigates the influence on the grid-connected PV system from aspect of power quality, i.e. voltage drop. This paper includes four MPPT algorithms; Perturbation & Observation(P&O), Improved P&O, Increment Conductance(Incond), Hysterisis simulated with irradiation changing.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.2
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• pp.109-115
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• 2014

Analyzing large scale data has become an important activity for many organizations. Since MapReduce is a promising tool for processing the massive data sets, there are increasing studies to evaluate the performance of various algorithms related to MapReduce. In this paper, we first develop a simulation framework that includes MapReduce workload model, data center model, and the model of data access pattern. Then we propose two algorithms that can reduce the energy consumption of MapReduce systems. Using the simulation framework, we evaluate the performance of the proposed algorithms under different application characteristics and configurations of data centers.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.4
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• pp.243-248
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• 2011

A FFT/IFFT processor is the key component for orthogonal frequency division multiplexing (OFDM) systems based IEEE 802.11n wireless local area network (WLAN). There exists many radix algorithms according to the structure of butterfly as FFT sub-module, each has the pros and cons on hardware complexity. Here, mixed radix algorithms for 64 and 128 FFT/IFFT processors are proposed, which reduce hardware complexity by using mixture of radix-23 and radix-4 algorithms. The proposed algorithm finish calculation within 3.2${\mu}s$ in order to meet IEEE 802.11n standard requirements and it has less hardware complexity compared with conventional algorithms.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.289-292
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• 1998

Trees are the underlying structure for divide-and-conquer algorithms and the graphs that provide the solution spaces for NP-complete problems. Complete binary trees are the basic structure among trees. Therefore, if complete binary trees can be embedded in binomial trees, the algorithms which are provided by complete binary trees can be performed efficiently on the interconnection networks which have binomial trees as their subgraphs or in which binomial trees can be embedded easily. In this paper, we present dilation 2 embedding of complete binary trees in binomial trees.

• Journal of Broadcast Engineering
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• v.19 no.3
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• pp.316-328
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• 2014

In this paper, we parallelize the popular feature detection algorithms, i.e. SIFT and SURF, and its application to fast panoramic image generation on the latest embedded GPU. Parallelized algorithms are implemented using recently developed OpenCL as the embedded GPGPU software platform. We compare the implementation efficiency and speed performance of conventional OpenGL Shading Language and OpenCL. Experimental result shows that implementation on OpenCL has comparable performance with GLSL. Compared with the performance on the embedded CPU in the same application processor, the embedded GPU runs 3~4 times faster. As an example of using feature extraction, panorama image synthesis is performed on embedded GPU by applying image matching using detected features.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.273-283
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• 2008

Many embedded real-time systems have adopted processors supported with dynamic voltage scaling(DVS) recently. Power is one of the important metrics for optimization in the design and operation of embedded real-time systems. We can save considerable energy by using slowdown of processor supported with DVS. In this paper, we propose heuristic algorithms to calculate task slowdown factors for an efficient energy consumption in embedded real-time systems with task synchronization. The previous algorithm has a following constraint : given the tasks are ordered in a nondecreasing order of their relative deadline, the task slowdown factors computed are in a nonincreasing order. In this paper, we relax the constraint and propose heuristic algorithms which have the same time complexity that previous algorithm has and can save more energy. Experimental results show that the proposed algorithms are energy efficient.