• 제목/요약/키워드: Electronics Industry

검색결과 1,320건 처리시간 0.049초

잠수함용 LED 등기구의 제작과 평가 (Fabrication and Evaluation of a LED Luminaire for Submarine)

  • 김선재;김세진;길경석;안창환;송동영
    • 한국전기전자재료학회논문지
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    • 제26권10호
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    • pp.778-784
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    • 2013
  • In order to develop a LED luminaire for naval-submarines which can replace a conventional one with two-compact fluorescent lamp (CFL) of 18 W, we analyzed the electrical and optical performance of the conventional luminaire. A LED luminaire was fabricated as compact as possible based on the analyzed data. The weight of the prototype LED luminaire is 1.8 kg, reducing up to 58% of the conventional one. The use of LED package for the submarine luminaire could reduce the power consumption from 38 W to 14.5 W with the same optical performance. The reason is that the optical efficacy of the LED luminaire improved by 2.47 times as 61.9 lm/W, compared to 25.1 lm/W for the conventional one.

Cl2/HBr/CF4 반응성 이온 실리콘 식각 후 감광막 마스크 제거 (Removal of Photoresist Mask after the Cl2/HBr/CF4 Reactive Ion Silicon Etching)

  • 하태경;우종창;김관하;김창일
    • 한국전기전자재료학회논문지
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    • 제23권5호
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    • pp.353-357
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    • 2010
  • Recently, silicon etching have received much attention for display industry, nano imprint technology, silicon photonics, and MEMS application. After the etching process, removing of etch mask and residue of sidewall is very important. The investigation of the etched mask removing was carried out by using the ashing, HF dipping and acid cleaning process. Experiment shows that oxygen component of reactive gas and photoresist react with silicon and converting them into the mask fence. It is very difficult to remove by using ashing or acid cleaning process because mask fence consisted of Si and O compounds. However, dilute HF dipping is very effective process for SiOx layer removing. Finally, we found optimized condition for etched mask removing.

An Analysis on the Selection Process of Core Wireless Communications Technologies in Korean National IT R&D Program

  • Ilsue Roh;Lee, Byoung-Nam;Lee, Jungman
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -2
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    • pp.1320-1323
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    • 2002
  • This paper reviews the Korean government’s selection process of core wireless communications technologies, and presents technology trends, perspectives and strategies of 5 core technologies to develop in wireless communications areas based on the mid term IT technology development plan(2002∼2004). Delphi Panel Method and Analytic Hierarchy Process(AHP) Analysis were adapted to select 30 core technologies in 9 strategic areas. Especially, 5 core wireless communications technologies out of 24 required technologies are selected: 4 G Core Technology, Broadband Wireless Access Network Technology, IMT-2000 Plus STP Technology, OBP Based Multimedia Satellite Communications Technology, Stratosphere Communications System Technology. Strategic national IT R&D program has been essential to continue success story of CDMA technology, and acquiring technology independency from advanced nations. In long term perspectives, a strategy of intensive investment with prudent selection onto core technologies should be deployed in the IT R&D programs. Also, the national IT R&D programs should be limited in the high risk & high returen areas where only government can afford the failures as well as better spill over effects are expected for the technology development and national economy. Korean industry has some strength in wireless communications technology area. Therefore, more policy concerns should be given into this area not only to secure present strength but also to explore better technology competitiveness.

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Fabrication of Core-Shell Structure of Ni/Au Layer on PMMA Micro-Ball for Flexible Electronics

  • Hong, Sung-Jei;Jeong, Gyu-Wan;Han, Jeong-In
    • Current Photovoltaic Research
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    • 제4권4호
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    • pp.140-144
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    • 2016
  • In this paper, core-shell structure of nickel/gold (Ni/Au) conductive layer on poly-methyl-methacrylate (PMMA) micro-ball was fabricated and its conduction property was investigated. Firstly, PMMA micro-ball was synthesized by using dispersion polymerization method. Size of the ball was $2.8{\mu}m$ within ${\pm}7%$ deviation, and appropriate elastic deformation of the PMMA micro-ball ranging from 31 to 39% was achieved under 3 kg pressure. Also, 200 nm thick Ni/Au conductive layer was fabricated on the PMMA micro-ball by uniformly depositing with electroless-plating. Adhesion of the conductive layer was optimized with help of surface pre-treatment, and the layer adhered without peeling-off despite of thermal expansion by collision with accelerated electrons. Composite paste containing core-shell structured particles well cured at low temperature of $130^{\circ}C$ while pressing the test chip onto the substrate to make electrical contact, and electrical resistance of the conductive layer showed stable behavior of about $6.0{\Omega}$. Thus, it was known that core-shell structured particle of the Ni/Au conductive layer on PMMA micro-ball was feasible to flexible electronics.

디바이스 내장형 플렉시블 전자 모듈 제조 및 신뢰성 평가 (Fabrication and Reliability Test of Device Embedded Flexible Module)

  • 김대곤;홍성택;김덕흥;홍원식;이창우
    • Journal of Welding and Joining
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    • 제31권3호
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    • pp.84-88
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    • 2013
  • These days embedded technology may be the most significant development in the electronics industry. The study focused on the development of active device embedding using flexible printed circuit in view of process and materials. The authors fabricated 30um thickness Si chip without any crack, chipping defects with a dicing before grinding process. In order to embed chips into flexible PCB, the chip pads on a chip are connected to bonding pad on flexible PCB using an ACF film. After packaging, all sample were tested by the O/S test and carried out the reliability test. All samples passed environmental reliability test. In the future, this technology will be applied to the wearable electronics and flexible display in the variety of electronics product.

근접장 전기방사 방식을 이용한 Ag 미세 패턴 형성 (A Study on fabrication of the Ag fine pattern using Near Field Electro Spinning(NFES))

  • 심효선;서화일;윤두협
    • 반도체디스플레이기술학회지
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    • 제10권4호
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    • pp.65-70
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    • 2011
  • These days, printed electronics attract attention from electronics industry. In this paper, the fabrication of the fine patterns by Near Field Electro Spinning (NFES) was studied by using Ag ink on silicon wafer (substrate). Two types of ink, the high viscous ink Ag-200 and low viscous ink Ag-15, were used. The fine and uniform patterns were easily fabricated by using Ag-200 because jet breakup is less occurred in high viscosity solution. As increasing flow rate of solution, aspect ratio of Ag pattern decreased. And there was optimum applied voltage for fine pattern. In case of Ag-200, the optimum applied voltage was about 2.02KV. When pattern was fabricated by NFES, the pattern width and height were affected by many factors such as viscosity, flow rate of solution, applied voltage etc.

Atmospheric Plasma Treatment on Copper for Organic Cleaning in Copper Electroplating Process: Towards Microelectronic Packaging Industry

  • Hong, Sei-Hwan;Choi, Woo-Young;Park, Jae-Hyun;Hong, Sang-Jeen
    • Transactions on Electrical and Electronic Materials
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    • 제10권3호
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    • pp.71-74
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    • 2009
  • Electroplated Cu is a cost efficient metallization method in microelectronic packaging applications. Typically in 3-D chip staking technology, utilizing through silicon via (TSV), electroplated Cu metallization is inevitable for the throughput as well as reducing the cost of ownership (COO).To achieve a comparable film quality to sputtering or CVD, a pre-cleaning process as well as plating process is crucial. In this research, atmospheric plasma is employed to reduce the usage of chemicals, such as trichloroethylene (TCE) and sodium hydroxide (NaHO), by substituting the chemical assisted organic cleaning process with plasma surface treatment for Cu electroplating. By employing atmospheric plasma treatment, marginally acceptable electroplating and cleaning results are achieved without the use of hazardous chemicals. The experimental results show that the substitution of the chemical process with plasma treatment is plausible from an environmentally friendly aspect. In addition, plasma treatment on immersion Sn/Cu was also performed to find out the solderability of plasma treated Sn/Cu for practical industrial applications.

Experimental Characterization-Based Signal Integrity Verification of Sub-Micron VLSI Interconnects

  • Eo, Yung-Seon;Park, Young-Jun;Kim, Yong-Ju;Jeong, Ju-Young;Kwon, Oh-Kyong
    • Journal of Electrical Engineering and information Science
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    • 제2권5호
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    • pp.17-26
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    • 1997
  • Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

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A Novel Three Phase Series-Parallel Resonant Converter Fed DC-Drive System

  • Daigavane, Manoj;Suryawanshi, Hiralal;Khan, Jawed
    • Journal of Power Electronics
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    • 제7권3호
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    • pp.222-232
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    • 2007
  • This paper presents the application of a single phase AC-to-DC converter using a three-phase series parallel (SPRC) resonant converter to variable speed dc-drive. The improved power quality converter gives the input power factor unity over a wide speed range, reduces the total harmonic distortion (THD) of ac input supply current, and makes very low ripples in the armature current and voltage waveform. This soft-switching converter not only possesses the advantages of achieving high switching frequencies with practically zero switching losses but also provides full ranges of voltage conversion and load variation. The proposed drive system is the most appropriate solution to preserve the present separately excited de motors in industry compared with the use of variable frequency ac drive technology. The simulation and experimental results are presented for variable load torque conditions. The variable frequency control scheme is implemented using a DSP- TMS320LF2402. This control reduces the switching losses and current ripples, eliminates the EMI and improves the efficiency of the drive system. Experimental results confirm the consistency of the proposed approach.

Industrial IoT를 위한 데이터베이스 접근 기반 장비 제어 시스템 개발 (Development of Equipment Control System based on DB Access Method for Industrial IoT)

  • 조경우;전민호;오창헌
    • 한국정보통신학회논문지
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    • 제20권6호
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    • pp.1142-1147
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    • 2016
  • 최근 다양한 분야에 걸쳐 ICT 기술을 융합하여 지능적인 서비스를 제공하는 IoT에 대한 다양한 연구가 진행되고 있다. 특히 독일의 'Industry 4.0'의 등장으로 제조 산업에 ICT를 융합하여 생산능력을 극대화 하는 industrial IoT의 중요성이 강조되고 있다. 이에 국내에서도 industrial IoT의 근간이 되는 스마트 팩토리 보급을 위한 다양한 노력이 진행 중이다. 그러나 현재의 스마트 팩토리 시스템은 장비의 임베디드 시스템에 선언된 데이터를 통해 설비를 제어하며, 다수의 설비가 배치되어 있는 환경에 대처하기 어렵다. 본 논문에서는 industrial IoT를 위해 장비의 변수 정보를 DB화하여 장비를 제어하는 데이터베이스 접근 기반 장비 제어 시스템을 제안한다. 제안하는 시스템을 다양한 변수가 존재하는 사출 시스템에 적용하여 데이터베이스의 수정으로 다수의 장비를 제어하는데 효율적임을 확인하였다.