• Journal of the Korean Society for Precision Engineering
• /
• v.31 no.10
• /
• pp.865-871
• /
• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Journal of Welding and Joining
• /
• v.30 no.3
• /
• pp.21-25
• /
• 2012

• Journal of the Microelectronics and Packaging Society
• /
• v.11 no.3 s.32
• /
• pp.55-62
• /
• 2004

The oxidation of pure Sn and high Pb-Sn alloys was investigated under different oxidizing conditions of temperature and humidity. Both the chemical nature and the amount of oxides were characterized using electrochemical reduction analysis by measuring the electrolytic reduction potential and total transferred electrical charges. For pure tin, SnO grew faster under humid condition than in dry air at $85^{\circ}C$. A very thin (<10 ${\AA}$) layer of SnO, was formed on the top surface under humid condition. The mixture of SnO and $SnO_2$ was found for oxidation at $150^{\circ}C$. XPS and AES were performed to support the result of oxide reduction.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.1
• /
• pp.33-37
• /
• 2008

A noticeable amount of Kirkendall voids formed at the Sn-3.5Ag solder joint with electroplated Cu, and that became even more significant when an additive was added to Cu electroplating bath. With SPS, a large amount of voids formed at the $Cu/Cu_3Sn$ interface of the solder joint during thermal aging at $150^{\circ}C$. The in-situ AES analysis of fractured joints revealed S segregation on the void surface. Only Cu, Sn, and S peaks were detected at the fractured $Cu/Cu_3Sn$ interfaces, and the S peak decreased rapidly with AES depth profiling. The segregation of S at the $Cu/Cu_3Sn$ interface lowered interface energy and thereby reduced the free energy barrier for the Kirkendall void nucleation. The drop impact test revealed that the electrodeposited Cu film with SPS degraded drastically with aging time. Fracture occurred at the $Cu/Cu_3Sn$ interface where a lot of voids existed. Therefore, voids occupied at the $Cu/Cu_3Sn$ interface are shown to seriously degrade drop reliability of solder joints.

• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.4
• /
• pp.25-33
• /
• 2001

Sn-3.5Ag-xBi alloys with five different levels of Bi (0, 2.5, 4.8, 7.5, 10 wt%) were prepared for evaluating creep properties. Cast alloys were roiled and heat treated to provide stable microstructures during the subsequent creep tests, which were conducted under constant load using dog-bone specimens. For the Bi containing alloys, creep strength showed the maximum around 2.5 wt%Bi and tended to decrease with increasing Bi content. The stress exponent of the alloy was around 4, suggesting typical dislocation creep, but the exponent was 2 for the 10 wt%Bi alloy, suggesting creep assisted by grain boundary Sliding. For the Bi containing alloys, the brittle fracture mode appeared showing small amount of reduction of area, while the ductile fracture mode was true for the Bi free alloy. Microstructural examination of ruptured specimens showed cavitations on grain boundaries normal to the load axis, and a significant of grain boundary sliding for the Bi containing alloys.

• ETRI Journal
• /
• v.36 no.4
• /
• pp.617-624
• /
• 2014

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

• Journal of the Microelectronics and Packaging Society
• /
• v.16 no.1
• /
• pp.27-31
• /
• 2009

In this paper, the polymer adhesive bonding technology using wafer-level technology was investigated and warpage results were analyzed. Si and glass wafer was bonded after adhesive polymer layer and dam pattern for uniform state was patterned on glass wafer. In this study, warpage result decreased as the low of bonding temperature of Si wafer, bonding pressure and height of adhesive bonding layer. The availability of adhesive polymer bonding was confirmed by TC, HTC, Humidity soak test after dicing. The result is that defect has not found without reference to warpage.

• Journal of the Microelectronics and Packaging Society
• /
• v.28 no.1
• /
• pp.1-12
• /
• 2021

Here, we introduce a laser-induced graphene synthesis technology and its applications for the electric/electronic device manufacturing process. Recently, the micro/nanopatterning technique of graphene has received great attention for the utilization of these new graphene structures, which shows progress developments at present with a variety of uses in electronic devices. Some examples of practical applications suggested a great potential for the tunable graphene synthetic manners through the control of the laser set-up, such as a selection of the wavelength, power adjustment, and optical techniques. This emerging technology has expandability to electric/electronic devices combined together with existed micro-packaging technology and can be integrated with the new processing steps to be applied for the operation in the fields of biosensors, supercapacitors, electrochemical sensors, etc. We believe that the laser-induced graphene technology introduced in this paper can be easily applied to portable small electronic devices and wearable electronics in the near future.

• Proceedings of the Korean Society for Technology of Plasticity Conference
• /
• 2003.10a
• /
• pp.101-106
• /
• 2003

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole quality is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene Terephthalate) one. In this paper we found the correlation between hole quality and process condition such as ceramic thickness, and tool size. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• Journal of the Korean institute of surface engineering
• /
• v.32 no.3
• /
• pp.289-296
• /
• 1999

The integration of the LSI has been greatly improved and the circuit patters on the LSI are becoming finer line and pitch. The high-density electronic packaging technology is improved. In order to realize the high-density packaging technology, the density of the circuit wiring of the printed circuit boards have also been more dense. The build-up process multilayer printed circuit board technology have a lot of vias, possibilities of the finer conductor wirings and have a freedom of capabilities of wiring design. The build-up process printed circuit boards have the wiring rules which are the pattern width: $100-20\mu\textrm{m}$, the via hole diameter: $100-50\mu\textrm{m}$. There three kinds of build-up processes as far materials and hole drilling. In this paper, the recent technology trends of the build-up printed circuit board technologies are described.