• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.75-80
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• 2013

According to advance of electronic packaging technology, electronic package becomes smaller. Miniaturization of package causes the temperature rise of package. This can degrade life of electronic device and generate the failure of electronic system. In this study, we proposed a new semi-embedded structure with micro pattern for maximizing heat dissipation. A proposed structure showed the characteristics which have maximum temperature lower than $20^{\circ}C$ compared with conventional structure. And also, in view of thermal stress and strain, our structure showed a remarkably low value compared with other ones. We expect that the new structure proposed in this work can be applied to an flip-chip package of the future.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.30-41
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• 2023

With the aggressive down-scaling of advanced integrated circuits (ICs), electronic packages have become the bottleneck of both reliability and performance of whole electronic systems. In order to resolve the reliability issues, Institute of Electrical and Electronics Engineers (IEEE) laid down a roadmap on fault detection and diagnosis (FDD), thrusting the digital twin: a combination of reliability physics and artificial intelligence (AI). In this paper, we especially review research works regarding the signal-based FDD approaches on the electronic packages. We also discuss the research trend of FDD utilizing AI techniques.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.19-25
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• 2008

In this paper, the front end module (FEM) was proposed for 2.4GHz WLAN band by LTCC multilayer application. The FEM was composed of power amplifier IC, switch IC, and LTCC module. LTCC module consists of output matching circuit and lowpass filter as Tx part, bandpass filter as Rx part. Design of output matching circuit for LTCC was used matching parameter from output matching circuit based on lumped circuit on the PCB board. The dielectric constant of LTCC substrate is 9. The substrate was composed of total 26 layers with each 30um thickness. Ag paste was used for the internal pattern as the conductor material. The size of the module is $4.5mm{\times}3.2mm{\times}1.4mm$. The fabricated FEM showed the gain of 21dB, ACPR of less than -31dBc first side lobe and Less than -59dBc second side lobe and the output power of 23Bm at P1dB.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.61-73
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.19-28
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• 2016

This paper presents an overview of selected advanced measurement technologies for the mechanical properties of polymers used for flexible and stretchable electronic packaging. Over the years, a variety of flexible and stretchable electronics have been developed due to their potential applications for next generation IT industry. To achieve more flexible and wearable devices for practical applications, the usage of polymeric components has been increased significantly. Therefore, accurate measurement of mechanical properties of the polymers is necessary in order to design mechanically reliable devices. However, the measurement has been challenging due to the soft nature and thin applications of polymers. Here, we describe novel measurement technologies of mechanical properties of polymers for flexible and stretchable electronics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.212-212
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• 2008

에폭시 수지는 화학적 열적 안정성과 절기 절연성 및 기계적 특성 등 여러 가지 우수한 특성에도 불구하고 난연성은 그 단독으로 만족시킬 수 없기 때문에 난연제를 첨가함으로써 난연효과를 얻어왔다. 기존에 할로겐 화합물인 브롬계 난연제는 우수한 난연효과에도 불구하고 연소시 유해물질이 발생되어진다. 그리하여 인계 난연제를 첨가하는 것이 고분자 시스템에 난연성을 부여하는 효과적인 수단으로 대두되어지고 있다. 이 실험에서는 인계 난연제와 브롬계 난연제를 10, 20, 30, 40wt% 첨가하여 epoxy composite 제작하였다. 제작된 epoxy composite를 UL-94V 방법으로 난연성 평가하여 브롬계 난연제 20wt%에서 V-0를 획득할 수 있었으나 인계난연제 40wt%에서도 V-0를 만족할 수 없었다. 난연제 함량에 따른 Dielelctric constant 및 loss는 브롬계 난연제를 첨가시 감소하였고, 인계난연제의 경우 증가하였다.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.43-48
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• 2001

Economical consumption of energy, longer life of lamps, higher lighting comfort and new aesthetic of illumination is subject of numerous research and development works. The halogen lamps are an example of positive solution some of above mentioned problems. The electronic transformers are more frequent used for their supply. In comparison with conventional transformers they have less weight, less volume and 60% less power losses. Their advantages are particular visible, when the hybrid technique is applied. The paper presents the results of engineering research and development works carried out in Private Institute of Electronic Engineering, in R. & D. Center for Hybrid Microelectronics and Resistors and in Technical School of Communications in Krakow, in the field of the design and exploitation tests of hybrid converters 220V AC /12V DC (electronic transformers) and electronic ballasts destined for the supply of halogen lamps 20W to 150W and fluorescent lamps respectively. To perform the converters, thick film technology and surface mount technology were used. For the protection of converter electronic circuit the thick film temperature sensor and transistors were applied. Moreover the paper presents the base application circuits of elaborated converters, their technical parameters and exploitation results. The development perspectives of such domain of hybrid circuits are also discussed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.7-38
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• 2000

Performance, reliability, form factor drive flip chip use. BGAs and CSPs will provide stepping stone to FC DCA .Growing vendor infrastructure - Low cost, high density organic substrates -New generations of fluxes and underfills .Adhesives flip chip technology as a low cost flip chip alternatives -Low cost Au stud or Electroless Ni bumps -Reliable thermal cycling and electrical performance.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.51-69
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• 2001

Japan Jisso Technology Roadmap 2001 (JJTR2001) was published by JEITA in April 2001. Future electronic products request further higher assembly technology (ex. Finer pitch packages & components, 3D assembly, etc.) to reduce size and improve performance of the electric products. For LSI Packages, finer ball pitch technology and finer chip connection technology will be developed. For electric components, further size reduction will be developed. For Jisso (assembly) machine, finer pitch assembly and short tact time technology will be developed. Mr. Utsunomiya will present PCB roadmap next.