• 마이크로전자및패키징학회지
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• 제15권1호
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• pp.27-31
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• 2008

전자 부품의 소형화 요구에 따라서 기존 기판의 상부에 실장 되는 저항 소자를 감소하기 위한 방안으로 후막 저항 페이스트를 인쇄하여 저항체를 형성 한 후에 내장하는 수동소자 내장기술이 활발히 연구되고 있다. 본 연구에서는 카본 블랙과 에폭시 수지를 혼합하여 $0.35{\sim}4k{\Omega}/sq$으로 넓은 저항 범위를 가지는 저온 열경화형 후막 저항 페이스트를 제작하였으며, Ni-Cr alloy와 $SiO_2$ 분말을 첨가하여 온도에 따른 저항 변화인 TCR(Temperature Coefficient Resistivity) 값을 $100ppm/^{\circ}C$으로 개선하였다. 최종적으로 제작된 저항 페이스트를 이용하여 내장 저항 기판을 제작하였으며 온도에 변화에 따른 안정적인 저항 특성과 신뢰성을 확보 할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제11권4호
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• pp.178-181
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• 2010

An automotive IC voltage regulator which consists of one-chip based on a metal-oxide semiconductor field effect transistor (MOSFET) is investigated experimentally with three types of packaging. The closed type is filled with thermal silicone gel and covered with a plastic lid on the MOSFET. The half-closed type is covered with a plastic case but without thermal silicone gel on the MOSFET. Opened type is no lid without thermal silicone gel. In order to simulate the high temperature condition in engine bay, the operating circuit of the MOSFET is constructed and the surrounding temperature is maintained at $100^{\circ}C$. In the overshoot the maximum was mainly found at the half-closed packaging and the magnitude is dependent on the packaging type and the surrounding temperature. Also the impressed current decreased exponentially during the MOSFET operation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.99.1-99.1
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• 2016

The materials for an electronic packaging provide diverse important functions including electrical contact to transfer signals from devices, isolation to protect from the environment and a path for heat conduction away from the devices. The packaging materials composed of metals, ceramics, polymers or combinations are crucial to the device operating properly and reliably. The demand of effective charge and heat transfer continuous to be challenge for the high-speed and high-power devices. Nanomaterials including graphene, carbon nanotube and boron nitride, have been designed for the purpose of exploiting the high thermal, electrical and mechanical properties by combining in the matrix of metal or polymer. In addition, considering the inherent electrical and surface properties of graphene, it is expected that graphene would be a good candidate for the surface layer of a template in the electroforming process. In this talk, I will present recent our on-going works in nanomaterials for microelectronic packaging: 1) porous graphene/Cu for heat dissipations, 2) carbon-metal composites for interconnects and 3) nanomaterials-epoxy composites as a thermal interface materials for electronic packaging.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.313-313
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• 2008

Aerosol Deposition(AD) method is based on the impact consolidation phenomenon of ceramic fine particles at room temperature. AD is promising technology for the room temperature deposition of the dielectrics thin films with high quality. Embedding of passive components such as capacitors into printed circuit board is becoming an important strategy for electronics miniaturization and device reliability, manufacturing cost reduction. So, passive integration using aerosol deposition. In this study, we examine the effects of the characteristics of raw powder on the thickness, roughness, electrical properties of $BaTiO_3$ thin films. Thin films were deposited on the copper foil and copper plate. Electrical and material properties was investigated as a change of annealing temperature. We final aim the effects of before and after of laminated on the electrical properties and suit of embedded capacitor.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 추계 기술심포지움 초록집
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• pp.71-71
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• 2004

• Journal of Welding and Joining
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• 제22권4호
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• pp.24-28
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• 2004

마이크로 접합 공정은 미세 부품이나 박판의 접합에 사용되며, 이를 위해 다양한 공정이 개발되었다. 최근 MEMS(Micro Electro Mechanical System)활용 범위가 증가하고 있으며, MEMS에 사용되는 미세한 구조물의 접합이나 패키징에 접합 공정이 활용되고 있다. MEMS는 발전 단계이지만 전자 패키징(electronic packaging)은 성숙 단계인 반도체 산업에 사용되고 있다.(중략)

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.731-732
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• 2011

• 마이크로전자및패키징학회지
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• 제28권4호
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• pp.97-101
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• 2021

본 연구에서는 실험 설계법을 통해 인터포저에서 Through Silicon Via (TSV) 및 Redistributed Layer (RDL)의 구조적 변형에 따른 삽입 손실 특성 변화를 확인하였다. 이때 3-요인으로 TSV depth, TSV diameter, RDL width를 선정하여, 구조적 변형을 일으켰을 때 400 MHz~20 GHz에서의 삽입 손실을 EM (Electromagnetic) tool Ansys HFSS(High Frequency Simulation Software)를 통해 확인하였다. 반응 표면법을 고려하였다. 그 결과 주파수가 높아질수록 RDL width의 영향이 감소하고 TSV depth와 TSV diameter의 영향이 증가하는 것을 확인했다. 또한 분석 범위 내에서 RDL width를 증가시키면서 TSV depth를 감소시키고 TSV diameter를 약 10.7 ㎛ 고정하는 것이 삽입 손실을 가장 최적화 시키는 결과가 관찰되었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.23-34
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• 2005

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

• E2M - 전기 전자와 첨단 소재
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• 제16권7호
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• pp.3-13
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• 2003