• 마이크로전자및패키징학회지
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• 제11권4호
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• pp.75-80
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• 2004

In copper metallization, resistivity of copper seed layer is very important. Conventionally MOCVD has been used for this purpose however electroless copper plating is simple process and the resistivity of copper deposit is less than that of copper prepared by MOCVD. In this study electroless copper plating was conducted on different substrate to find optimum conditions of electroless copper plating for electronic applications. To find optimum conditions, the effects and selectivity of activation method on several substrates were investigated. The effects of copper bath composition on morphology were investigated. The effects of pH and stabilizer on deposition rate were also investigated. The optimum pH of the bath was 12 with addition of stabilizer. The resistivity of copper was decreased with addition of stabilizer and alter heat treatment.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.332-336
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• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional Pt layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at $330^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• 마이크로전자및패키징학회지
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• 제4권2호
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• pp.1-16
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• 1997

Modern electronic components require its sophistication to meet the stringent requirements which are demanded for high tech industry. In an attempt to meet to such demand miniaturization of the components has been considrably progressed to increase its circuit density. High density of the components can be achieved by an innovative technology of design and manufacturing with functionally improved or new materials such as small bulk devices thick films and thin films circuits (2D). Recently many efforts have been extensively made in the community of the Hybrid Microelectronics through out world. In this paper an approach is introduced in realizing a sophisticated passive circuit for the microelectronics applications by use of hybrid thick/thin films technology. The merit of this technology is discussed and the future trend is speculated.

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.9-16
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• 2012

Currently due to increasing integration of various electronic devices and need of multi-functions, more and more heat is produced and for electronic devices to achieve maximum performance with optimum life time, heat dissipation is critical. A solution to such problems is use of high heat dissipative insulating sheet. In this paper status of current products are introduced and several technology aspects to meet the demand of increased heat dissipation needs is introduced.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• 한국복합재료학회:학술대회논문집
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• 한국복합재료학회 2000년도 추계학술발표대회 논문집
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• pp.58-62
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• 2000

The fabrication process and analysis of thermal properties of 50~76vo1% SiCp/Al metal matrix composites(MMCs) for heatsink materials in electronic packaging were investigated. The 50~76vo1% SiCp/Al MMCs fabricated by pressure infiltration casting process showed that thermal conductivities were 85~170W/mK and coefficient of thermal expansion(CTE) were ranged 10~6ppm1k. Specially, the thermal conductivity and CTE of 71vo1%SiCp/Al MMCs were ranged 115~156W/mK and 6~7ppm/K. respectively, which showed a improved thermal properties than the conventional electronic packaging materials such as ceramics and metals.

• ETRI Journal
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• 제36권4호
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• pp.617-624
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• 2014

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

• 마이크로전자및패키징학회지
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• 제26권4호
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• pp.15-22
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• 2019

Metallic nanowires (MNWs) have recently been considered as one of the most promising candidates for flexible electrodes of advanced electronics including wearable devices, electronic skins, and soft robotics, since they have high aspect ratio in physical shape, low percolation threshold, high ductility and optical transparency. Herein, we review the latest findings related to the MNWs and discuss the properties and potentials of this material that can be used in implementation of various advanced electronic devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
• /
• pp.332-336
• /
• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional R layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at 330$^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.2395-2397
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• 2005

A low voltage operated piezoelectric RF MEMS in-line switch has been realized by using silicon bulk micromachining technologies for advanced mobile/wireless applications. The developed RF MEMS in-line switches were comprised of four piezoelectric cantilever actuators with an Au contact metal electrode and a suspended Au signal transmission line above the silicon substrate. The measured operation dc bias voltages were ranged from 2.5 to 4 volts by varying the thickness and the length of the piezoelectric cantilever actuators, which are well agreed with the simulation results. The measured isolation and insertion loss of the switch with series configuration were -43dB and -0.21dB (including parasitic effects of the silicon substrate) at a frequency of 2GHz and an actuation voltage of 3 volts.