• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.407-411
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• 2000

Low-temperature solder glass for use in electronic package was experimentally prepared and its crystallization behavior was investigated using differential thermal analysis (DTA) under nonisothermal condition. The composition of the solder glass was determined from PbO-ZnO-$B_2$$O_3$-$TiO_2$ glasses containing small amounts of CaO, $SiO_2$$A1_2$$O_3$ and $P_2$$O_5$. The crystallization exotherm corresponding to the formation of lead titanate (PbTiO$_3$) was observed. The crystallization of $PbTiO_3$was a three-dimensional process with the average activation energy of 223$\pm$3 kJ/mol for the crystallization from the glass matrix.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.63-67
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• 2021

In order to detect fires that may not be visible to the naked eye, an IoT module that uses changes in Carbon dioxide (CO₂) levels and temperature to effectively identify ambers (dying flames) was developed. Finite element analysis was then used to optimize the packaging for this module. Given the nature of ambers, the low power long range LoRa (Long Range) technology was used in the development of this module. To protect the module, a number of packages were designed, and comparative analysis performed on the stress generated when they fall. The results of which show that Model C showed the lowest stress. In addition, unlike other models in which stress concentration was predicted in the module mounting part of the package, in this model the stress concentration phenomenon was predicted in the wing part. It was therefore determined that this approach is ideal for protecting the internal module, and a package to which this was applied was manufactured.

• Transactions on Electrical and Electronic Materials
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• v.15 no.4
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• pp.221-225
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• 2014

Although gold wire bonding techniques have already matured in semiconductor manufacturing, weakly bonded wires in semiconductor chip assembly can jeopardize the reliability of the final product. In this paper, weakly bonded or failed aluminum bonding pads are analyzed using X-ray photoelectron spectroscopy (XPS), Auger electron Spectroscopy (AES), and energy dispersive X-ray analysis (EDX) to investigate potential contaminants on the bond pad. We found the source of contaminants is related to the dry etching process in the previous manufacturing step, and fluorocarbon plasma etching of a passivation layer showed meaningful evidence of the formation of fluorinated by-products of $AlF_x$ on the bond pads. Surface analysis of the contaminated aluminum layer revealed the presence of fluorinated compounds $AlOF_x$, $Al(OF)_x$, $Al(OH)_x$, and $CF_x$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.49-54
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• 1993

This paper discusses the reliability of solder joints of electronic devices on printed circuit board. Solder application is usually done by screen printing method for the bonding between outer leads of devices and thick film(Ag/Pd) pattern on Hybrid IC as wel1 as Cu lands on PCB. As result of thermal stresses generated at the solder joints due to the differences of thermal expansion coefficients between packge body and PCB, Micro cracking often occurs due to thermal fatigue failure at solder joints. The initiation and the propagate of solder joint crack depends on the environmental conditions, such as storage temperature and thermal cycling. The principal mechanisms of the cracking pheno- mana are the formation of kirkendal void caused by the differences in diffusion rate of materials, ant the thermal fatigue effect due to the differences of thermal expansion coefficient between package body and PCB. Finally, This paper experimentally shows a way to supress solder joints cracks by using low-${\alpha}$ PCB and the packages with thin lead frame, and investigates the phenomena of diffusion near the bonding interfaces.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.1142-1144
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• 1999

A 4-beam cross type silicon elastic body was fabricated for the electromagnetic type vibration micro transducer. To improve energy transfer efficiency, the structure and size of vibration transducer were optimized by the FEA simulation package. Experimental results of the fabricated transducer shows $0.5{\sim}8$ dyne of vibration force at the condition of $1{\sim}4$ mA of current source $100{\sim}7000$ Hz of frequency band width. These results presented the useful applications for micro actuators and sensors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.348-348
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• 2008

In recent, the concept of system-on-package (SOP) for highly integrated multifunctional systems has been paid attention to for the miniaturization and high frequency of electronic devices. In order to realize SOP, co-integration of passive devices, such as capacitors, resistors and inductors, and active devices should be achieved. If ceramic thick films can be grown at room temperature, we expect to be able to overcome many problems in conventional fabrication processes. So, we focused on the aerosol deposition method (ADM) as room temperature fabrication technology. ADM is a novel ceramic coating method based on the Room Temperature Impact Consolidation (RTIC) phenomena. This method has a wide range potential for fabrication of co-integration of passive and active devices. In this paper, I will present the future potential of ADM introducing various ceramic dielectric thick films for the integration of electronic ceramics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• Korean Journal of Computational Design and Engineering
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• v.9 no.4
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• pp.416-424
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• 2004

In this paper, the heat transfer analysis and thermal stress analysis of the PCB(Printed Circuit Board) equipped in electronic Packages are carried out for various may types of chips on the PCB. And two structural PCB models are used in the analyses. The electronic chips on the PCB usually emit heat and this heat generates the thermal stress around the chip. The thermal load due to the heat generation of chips on the PCB may cause the malfunction of the electronic packages such as a monitor. a computer etc. Hence, the PCB should be designed to withstand these thermal loads. In this paper, the heat transfer analysis and thermal stress analysis are executed for the PCB model with pins and the analysis results are compared with the results for the PCB model without pins. The analysis results show that the PCB model without pins is not good for the thermal stress analysis of PCB, even though these two models have similar heat transfer characteristics. The analysis results also show that the highest thermal stress occurs in the pin especially attached to the highest temperature chip, and the PCB constrained to the electronic package on the long side is structurally more stable than other cases. The analyses of the PCB are executed using the finite element analysis code, NISA.

• Proceedings of the Korean DIstribution Association Conference
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• 2002.05a
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• pp.31-59
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• 2002

Recently there are many changes of logistics environment Such as integrated logistics information system, the rapid growth of the domestic and international small package express service and third party logistics with Electronic Commerce. At this time it is very important to deliver to customers the goods sold through EC speedy, accurately and safely. That is to say, the role of small package express service is very important at EC times. The bottlenecks of small package express service in the circumstances of EC are the weakness of EC operating company and small package express service provider the shortage of distribution centre and cargo terminal, the shortage of skilled man with related small package express service etc. So, I suggested that for activation of EC it is necessary to strengthen the strategic alliances, introduce GPS and use the third party logistics positively in the side of small package express service provider. And it is necessary to prepare for the settlements of traffic problems, support the introduction of integrated logistics service, logistics information system, deregulate restriction such as weight limit of vehicles in the side of the government. And to government support throughout extending nation's SOC, deregulation, support to small package express service terminal, permit to stopping & parking in downtown, abolishing a no passing zone, permit to being employed foreigner. Also this service involves ensuring that the product will arrive when wanted, and in an undamaged condition.

• Journal of the Korean Ceramic Society
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• v.26 no.6
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• pp.829-835
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• 1989

Devitrifing solder glasses in a specific group of glass ceramic materials are extensively used in hermetically sealing alumina electronics packages. Preferred frit glass compositions of this study consist of 37~40wt% PbO, 35~40wt% ZnO, 18~20wt% B2O3, 1~3wt% SiO2, 0~6wt% TiO2. The coated frit glasses crystallize during firing and form a strong hermetic seal. DTA and X-ray diffraction were used to characterize crystallization of the glass frit. Frit seal containing 2wt% TiO2 has crystallization temperature of 550~57$0^{\circ}C$ with surface nucleation. Frit seal containing 6wt% TiO2 has crystallization temperature of 515~5$25^{\circ}C$ with bulk nucleation, and the main crystalline phase was perovskite lead titanate having minus expansion coefficient. The average activation energy for the crystallization calculated from Ozawa equation was 65$\pm$10kcal/mol.