• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.12
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• pp.2503-2510
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• 2015

This paper presents a single-phase energy measurement IC to measure electric power quantities. The entire IC includes two programmable gain amplifiers (PGAs), two ${\sum}{\Delta}$ modulators, a reference circuit, a low-dropout (LDO) regulator, a temperature sensor, a filter unit, a computation engine, a calibration control unit, registers, and an external interface block. The proposed energy measurement IC is fabricated with $0.18-{\mu}m$ CMOS technology and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4,096 kHz and consumes 10 mW in 3.3 V supply.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.2
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• pp.158-163
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• 2013

In this paper, thermal analysis of heatsink for 30 W class Chip-on-Board (COB) LED light source is performed by using SolidWorks Flow Simulation package. In order to increase the convection heat transfer, number of fin and shape of the heatsink is optimized. Furthermore, a copper spread is applied between the COB LED light source and the heatsink to mitigate the heat concentration on the heatsink. With the copper spread, the junction temperature between the COB LED light source and the heatsink is $50.9^{\circ}C$, which is $5.4^{\circ}C$ lower than the heatsink without the copper spread. Due to the improvement of the junction temperature, the light output is improved by 5.8% when the LED light source is stabilized. The temperature difference between the simulation and measured result of the heatsink with the copper spread is within $2^{\circ}C$, which verifies the validity of the thermal design method using a simulation package.

• Journal of Korean Society for Quality Management
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• v.40 no.3
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• pp.286-294
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• 2012

Purpose: In this study, we propose the ESS process model which, in order to improve reliability of electronic equipment, can be referenced in both development and production phases. Methods: ESS guidelines such as MIL handbooks or private sector ESS guidelines are used for devising the proposed ESS model. Especially, proposed model is customized by using those references in order to be optimized in the domestic development and production phases. Results: ESS-related-requirements which is specified in the Technical Data Package(TDP) for the area of guided missile systems are analyzed. Current status of the requirement and screening strength are analyzed for those systems to show what kind of weak points should be improved. Conclusion: A ESS guideline which is applicable to the domestic weapon acquisition environment is proposed. As such, the necessity and detail guidelines of the proposed model are explained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.205-208
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• 2001

Steady state and transient thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage for microwave oven. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally copper wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin and epoxy with a thickness of $25{\mu}m$ and $3700{\mu}m$, respectively. The chip size, thickness and material properties were very important factor for high voltage diode package. And also, thermal stress value was highest in the edge of diode and solder. So, design of edge in silicon was very important to thermal stress.

• Journal of Mechanical Science and Technology
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• v.15 no.1
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• pp.98-107
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• 2001

Continuing efforts to achieve increased circuit performance in electronic package have resulted in higher power density at chip and module level. As a result, the thermal management of electronic package has been important in maintaining or improving the reliability of the component. An experimental investigation of thermosyphonic boiling in vertical tube and channel made by two parallel rectangular plates was carried out in this study for possible application of the direct immersion cooling. Fluorinert FC-72 as a working fluid was used in this experiment. Asymmetric heated channel of open periphery with gap size of 1, 2, 4 and 26mm and uniformly heated vertical tubes with diameter of 9, 15 and 20mm were boiled at saturated condition. The boiling curves from tested surfaces exhibited the boiling hysteresis. It was also found that the gap size is not a significant parameter for the thermosyphonic boiling heat transfer with this Fluorinert. Rather pool boiling characteristics appeared for larger gap size and tube diameter. The heat transfer coefficients measured were also compared with the calculation results by Chens correlation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.205-208
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• 2001

Steady state and transient thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage for microwave oven. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally copper wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin and epoxy with a thickness of 25$\mu\textrm{m}$ and 3,700$\mu\textrm{m}$, respectively. The chip size, thickness and material properties were very important factor for high voltage diode package. And also, thermal stress value was highest in the edge of diode and solder. So, design of edge in silicon was very important to thermal stress.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.575-579
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• 2004

Package reliability test was conducted to investigate the effect of solder paste composition at BGA Package. It was found that the shape and size of the phase form are affected by the processing parameters. The material have used to fill in the via was Sn/36Pb/2Ag and Sn/0.75Cu type solder paste. Sn/36Pb/2Ag and Sn/0.75Cu paste were fabricated on Tape-BGA substrates by screen printing process, and via ball mount data were characterized with variations of dwell time of 85 seconds at reflow peak temperature at 22$0^{\circ}C$ or 24$0^{\circ}C$. The test condition was MRT 30 $^{\circ}C$/60 %RH/96 HR. Failures formed of a ball-off in solder paste process were observed by using a Optical Microscope and SEM(Scanning Electron Microscope). It was concluded that intermetallic layer growth played important roles in increasing solder fatigue strength for addition of Ag composition. The degradation of shear strength of solder composition is discussed.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.57-65
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• 2015

Electronic packages consist of various materials, and as temperature changes, warpage occurs because of the difference in coefficient of thermal expansion. Shadow $moir{\acute{e}}$ is non-contact, whole field measurement technique for out-of-plane displacement. However, the technique has low sensitivity above $50{\mu}m/fringe$, it is not adequate for the warpage measurement in some circumstance. In this paper, by applying phase shifting process to the traditional shadow $moir{\acute{e}}$, measurement system having enhanced sensitivity of $12.5{\mu}m/fringe$ is constructed. Considering Talbot effect, the measurement is carried out in the half Talbot area. Shadow fringe pattern having four times enhanced sensitivity is obtained by the image process with four shadow fringes. The measurement technique is applied to the fibered package substrate and coreless package substrate for measuring warpages at room temperature and at about $100^{\circ}C$.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.9
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• pp.1408-1414
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• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.