• Journal of Information Technology Applications and Management
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• v.27 no.3
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• pp.19-36
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• 2020

The Internet of things (IoT) is a system of interrelated computed devices, digital machines and any physical objects which are provided with unique identifiers and the potential to transmit data to people or machine (M2M) without requiring human interaction. IoT devices can be used to monitor and control the electrical and electronic systems used in different fields like smart home, smart city, smart healthcare and etc. In this study we introduce four imaginary IoT devices as a learning support assistants according to students' dominant learning styles measured by Honey and Mumford Learning Styles: Activists, Reflectors, Theorists and Pragmatists. This research emphasizes the association between students' strong learning styles and a preference to appropriate IoT devices with specific characteristics. Moreover, different levels of IoT devices' architecture are clearly explained in this study where all the artificial devices are designed based on this structure. Data analysis of experiment were measured by the use of chi square test for association and research results showed the statistical significance of the estimated model and the impacts of each category over the model where we finally got accurate estimates for our research variables. This study revealed the importance of considering the students' dominant learning styles before inventing a new IoT device.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.486-486
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• 2013

Silicon nanowire devices fabricated by bottom-up methods are attracted due to their electrical, mechanical, and optical properties. Especially, to functionalize the surface of silicon nanowires by molecules has received interests. The changes in the characteristics of the molecules is delivered directly to the surface of the silicon nanowires so that the silicon nanowire can be utilized as an efficient read-out device by using the electronic state change of molecules. The surface treatment of the silicon nanowire with light-sensitive molecules can change its optical characteristics greatly. In this paper, we present the optical response of a SiNW field-effect-transistor (FET) conjugated with porphyrin molecules. We fabricated a SiNW FET and performed porphyrin conjugation on its surface. The characteristic and the optical response of the device shows a large difference after conjugation while there is not much change of the surface in the SEM observation. It attributed to the existence of few layer porphyrin molecules on the SiNW surface and efficient variation of the surface potential of the SiNW due to light irradiation.

• Journal of the Korean Society of Safety
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• v.17 no.4
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• pp.94-100
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• 2002

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipments need to be more alert to the problem of electrostatic discharges(ESD). In order to analyze damage characteristics of semiconductor device damaged by ESD, this study adopts a new charged-device model(CDM), field-induced charged model(FCDM) simulator that is suitable for rapid, routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. High voltage applied to the device under test is raised by the field of non-contacting electrodes in the FCDM simulator, which avoids premature device stressing and permits a faster test cycle. Discharge current and time are measured and calculated. The characteristics of electrostatic attenuation of domestic semiconductor devices are investigated to evaluate the ESD phenomena in the semiconductors. Also, the field charging mechanism, the device thresholds and failure modes are investigated and analyzed. The damaged devices obtained in the simulator are analyzed and evaluated by SEM. The results obtained in this paper can be used to prevent semiconductor devices form ESD hazards and be a foundation of research area and industry relevant to ESD phenomena.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2408-2413
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• 2007

Since the heat generation in a chip increases as the components are miniaturized and the computing speed becomes faster, suitable heat dissipation has become one of the primary limiting factors to ensure the reliable operation of the electronic devices. A pin-fin array could be used as an alterative cooling system of the electronic equipment. In this study, convective heat transfer through the pin-fin array is analyzed experimentally based on porous medium approach. The influence of the structure of the pin-fin array including the pin-fin spacing, the pin diameter and plate length on heat transfer characteristics is investigated and compared with the previous analytical results and existing correlation equations. Nowadays, electronic and mechanical devices become smaller and smaller. In this sense, the main purpose of this study is to decide the optimum pin-fin arrangement to get similar heat transfer performance when the length of the existing cooling system is reduced as a half.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1730-1733
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• 2004

Device miniaturization and high integrated circuit design is of major interest for the development of electronic devices. Various studies have been conducted to develop new material and processing technique[1]. Negative Differential Resistance(NDR) is the defining behavior in several electronic components, including the Esaki diode and most notably, resonant tunneling diodes(RTD)[2]. We made a comparison of electrical properties between 4,4-Di(ethynylphenyl)-2'-nitro-1-(thioacetyl)benzene and 4-[2,5-dimethoxy-4-(p henylethynyl)phenyl]ethynylphenylethanethioate, which have been well known as a conducting molecule having possible application to molecular level NDR devices. As a result, we measured current-voltage curves using Scanning Tunneling microscopy(STM), I-V curves also showed several current peaks between negative and positive bias region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.1
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• pp.16-20
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• 2020

In this study, a patterning method using self-aligned nanostructures was introduced to fabricate GaN-based fin-gate HEMTs with normally-off operation, as opposed to high-cost, low-productivity e-beam lithography. The honeycomb-shaped fin-gate channel width is approximately 40~50 nm, which is manufactured with a fine width using a proposed method to obtain sufficient fringing field effect. As a result, the threshold voltage of the fabricated device is 0.6 V, and the maximum normalized drain current and transconductance of Gm are 136.4 mA/mm and 99.4 mS/mm, respectively. The fabricated devices exhibit a smaller sub-threshold swing and higher Gm peak compared to conventional planar devices, due to the fin structure of the honeycomb channel.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.2
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• pp.179-184
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• 2010

The digital substation automation system has contributed hugely to increasing the stability of power systems by providing not only protection and control of power systems but diagnostic features alongside them. Digital substation automation systems in the scale of substations consist of integrated operation systems and intelligent electronic devices. The main intelligent electronic devices currently in use are digital protection relays and the bay controllers in Gas insulated switchgears. Proficiently accomplishing the coordination of protection within the power system as a means of ensuring reliability and contriving for the stability of power supply through connection of function, the application of bay controllers is crucial, which collectively manage the protection relay at the bay level in order to achieve both. In this research, the bay controllers to be used in high-voltage Gas insulated switchgear has been localized, and in particular, the logic function and editor required in order to minimize the complicated hardware-like cable connections in the local panel have been developed. In addition, to ensure the strength and reliability of the bay controller hardware developed herein, the type tests from KERI have been successfully completed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.207-207
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• 2008

Modern industry has focused on processing that produce low- loss dielectric substrates used complex micron-sized devices using tick film technologies such as tape casting and slip casting. However, these processes have inherent disadvantages fabricating high density interconnect with embedded passives for high speed communication electronic devices. Here, we have successfully fabricated porous alumina dielectric layer infiltrated with polymer solution by using inkjet printing process. Alumina suspensions were formulated as dielectric ink that were optimized to use in inkjet process. The layer was confirmed by field emission scanning electron microscope (FE-SEM) for measuring microstructure and volume fraction. In addition, the reaction kinetics and electrical properties were characterized by FT-IR and the impedance analyzer. The volume fraction of alumina in porous dielectric alumina layer is around 70% much higher than that in the conventional process. Furthermore, after infiltration on the dielectric layer using polymer resins such as cyanate ester. Excellent Q factors of the dielectric is about 200 when confirmed by impedance analyzer without any high temperature process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.6-14
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• 2012

For integrated complementary metal oxide semiconductor (CMOS) circuits, the lateral spread for two-dimensional (2-D) impurity distributions are very important for the analyzing the devices. The measured two-dimensional SEM data obtained using the chemical etching-method matched very well with the results of the Gauss model for boron implanted samples. But the profiles in boron implanted silicon were deviated from the Gauss model. The profiles in boron implanted silicon were shown a little bit steep profile in the deep region due to backscattering effect on the near surface from the bombardments of light boron ions. From the simulated 3-D data obtained using an analytical model, the 1-D and 2-D data were compared with the experimental data and could be verified the justification from the experimental data. The data of 3-D model were also shown good agreements with the experimental and the simulated data. It can be used in the 3-D chip design and the analysis of microelectro-mecanical system (MEMS) and special devices.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.592-601
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• 2016

This paper presents the modeling of insulated-gate bipolar transistor (IGBT) in electromagnetic transients program (EMTP) simulation for the reliable calculation of switching and conduction losses. The conventional approach considering the physical property of switching devices requires many attribute parameters and large computation efforts. In contrast, the proposed method uses the curve fitting and interpolation techniques based on typical switching waveforms and a user-defined component with variable resistances to capture the dynamic characteristics of IGBTs. Therefore, the simulation time can be efficiently reduced without losing the accuracy while avoiding the extremely small time step, which is required in simulation by the conventional method. The EMTP based simulation includes turn-on and turn-off transients of IGBT, saturation state, forward voltage of free-wheeling diode, and reverse recovery characteristics, etc. The effectiveness of proposed modeling for the EMTP simulation is verified by the comparison with experimental results obtained from practical implementation in hardware.