• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.37-47
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• 2011

Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.73-82
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• 2008

There are several approaches for reducing the ROB(Reorder Buffer) complexity in processors. The one technique that makes the simplest ROB ports relies on a distributed implementation that spreads the centralized ROB structure across the functional units(FUs). Each distributed buffers are decided on the size of them by workload of the functional units. The performance of the processor depends on the size of distributed ROB. However, most of previous works have depended on the simulation results to decide the optimsize of distributed ROB. In this Paper, we use an analytical model based on the M/M/1 Queuing theory to determine the optimum size of each distributed ROB. Our schemes are evaluated by using the simulation performed by the CPU2000 benchmarks. We are able to choose the optimum size of distributed ROB showing the 99.2% performance compared with existing superscalar processors. We can save 82% hardware resources in ports and reduce more than 30% of delay when ROB and distributed ROB proposed in this paper are designed by HDL.

• Journal of Biomedical Engineering Research
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• v.25 no.2
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• pp.119-127
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• 2004

In this paper, an automatic external biphasic defibrillator that removes ventricular fibrillation efficiently with a low discharging energy has been developed. The system is composed of software including a fibrillation detection algorithm and a system control algorithm, and hardware including a high voltage charging/discharging part and a signal processing part. The stability of the developed system has been confirmed through continuous charging/discharging test of 160 times and the detection capability of the real-time fibrillation detection algorithm has been estimated by applying a total of 30 various fibrillation signals. In order to verify the clinical efficiency and safety, the system has been applied to five pigs before and after fibrillation inductions. Also, we have investigated the system efficiency in removing fibrillation by applying two different discharging waveforms, which have the same energy but different voltage levels.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.3
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• pp.465-470
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• 2017

This paper designs and implements a smart garden system using probabilistic filter algorithm using SLAM that can be used in apartment or veranda. To do this, we used Arduino and environtal sensors, which are open hardware controllers, and designed to control and observe automatic water supply, lighting, and growth monitoring with three wireless systems (Bluetooth, Ethernet, WiFi). This system has been developed to make it possible to use it in an indoor space such as an apartment, rather than a large-scale cultivation system such as a conventional plant factory which has already been widely used. The developed system collects environmental data by using soil sensor, illuminance sensor, humidity sensor and temperature sensor as well as control through smartphone app, analyzes the collected data, and controls water pump, LED lamp, air ventilation fan and so on. As a wireless remote control method, we implemented Bluetooth, Ethernet and WiFi. Finally, it is designed for users to enable remote control and monitoring when the user is not in the house.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.1
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• pp.55-64
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• 2015

Wind turbine market is showed height growth rate of about 30% for year, and is increasingly growing. Total rate of domestic wind turbine installation is showing share of 0.2% of the global market that is 380MW. However, wind turbine installed in domestic are foreign product more than 90%. Similarly, Datalogger of pretest system for ocean wind turbine plant installation has been leaked huge cost to abroad by mostly abroad company product. In this paper, we proposed pretest weather resource measurement system for efficiency and investment cost cutting of wind turbine construction work. Preset weather resource measurement system is ocean weather resource measurement datalogger based on wireless communication(wifi) that have consist of hardware and software(wind rose) that is able to monitoring as datalogger of wireless bridge and battery state, wind direction, wind speed, temperature, humidity, radiation around weather tower and is able to analysis of measured data.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.224-232
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• 2018

According to government policy, renewable energy facility such as solar power generation is being implemented for newly constructed buildings. In recent years, the introduction of Energy Storage System (ESS) served as an emergency power for replacing an existing diesel generator has been increasing. Furthermore, in order to expand the efficacy of the ESS operation, operation in combination with renewable energy sources such as solar and wind power generation is increasing. Hence, development of the ESS operation algorithms for emergency mode as well as the peak power cut mode, which is the essential feature of ESS, are necessary. The operational scenarios of ESS need to consider load power requirement and the amount of the power generation by renewable energy sources. For the verification of the developed scenarios, tests under the actual situation are demanded, but there is a difficulty in simulating the emergency operation situation such as system failure in the actual site. Therefore, this paper proposes simulation models for the HILS(Hardware In the Loop Simulation) and operation modes developed through HILS for the ESS operated with renewable energy source under peak power reduction and emergency modes. The paper shows that the ESS operation scenarios developed through HILS work properly at the actual site, and it verifies the effectiveness of the control logic developed by the HILS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.79-84
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• 2006

This paper proposed a novel H.264 deblocking filter for low-power mobile multimedia SoCs. In H.264 deblocking filter, filtering can be skipped on some pixels when pixel value differences satisfy some specific conditions. Furthermore, whole filtering can be skipped when quantization parameter is less than 16. Based on these features, power consumption can be significantly reduced by shutting down deblocking filter partially or as a whole. The proposed deblocking filter can shut down partial or whole blocks with simple control circuits. Common hardware performs both horizontal filtering and vertical filtering. It was implemented in silicon chip using $0.35{\mu}m$ standard cell library technology. The gate count is about 20,000 gates. The maximum operation frequency is 108MHz. The maximum throughput is 30 frame/s with CCIR601 image format.