• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2067-2070
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• 2002

In this paper, a VLSI architecture for transform and quantization module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.62-68
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• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.

• Proceedings of the Korean Reliability Society Conference
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• 2006.05a
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• pp.3-19
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• 2006

The Status quo of the reliability in China is described in this paper, a reliability surge is now spreading in China, covering the fields such as hardware, software, machinery and electronics. The reliability work in China was firstly conducted by the CEPREI Lab as far as early in the 1950s, and the reliability engineering in China has developed from the reliability of electronic products to that of machinery and non-electronic products, from hardware reliability to software reliability, from the attention to the reliability statistical test to emphasis on the reliability engineering test. Concern of Chinese companies about the reliability is the complete import of reliability engineering, the reliability testing, the software reliability and the reliability of lead-free soldering. Demonstration of reliability cases is given.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.135-138
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• 2005

HDL(Hardware Description Language) is the most important modem tools used to describe hardware, and becomes important as we move to higher levels of abstraction. The HDL has been made brisk use of in analog design, MEMS device[1-2], process related field as well as digital design. The most important characteristics of HDL is Abstraction which is the strongest tool that extend greatly designer's design ability. In this paper by the Modelling Continuum with hierarchical structure of abstraction, we apply UML(Unified Modeling Language) to SoC Design with HDL UML makes an easy and visual description of the various levels of abstraction, and gives designers good flexible modeling capabilty for SoC Design.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• The Journal of Society for e-Business Studies
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• v.4 no.2
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• pp.81-94
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• 1999

This paper shows the architecture of IPS(Intermarket Payment System), an implementation of the electronic payment function for internet-shopping merchant system. Because the original purpose of commerce transaction is the exchange of money for goods or services, it is very important to prepare an exchangeable economic value or method. The electronic payment system is the hardware or software or both to process an electronic payment transaction. It has two type, the broker type and the electronic value type. The broker type means an intermediator between real bank network and internet commerce transaction. The electronic value type means a substitute for money in the real world. This paper shows the architecture and the function to implement the broker type electronic payment system. The system has two parts. One is the mediator part to support multiple payment systems and to offer common access methods for merchant system database. The other is the executor part to implement the payment protocol and to process payment transaction.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.56-63
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• 2007

A color gamut mapping has been known to be one of promising methods to enhance display quality of various types of color display device. However, it is required to handle this mapping in real time for display or digital TV application. If carefully arranged, the tetrahedral interpolation can be computed with simpler operations compared to a cubic interpolation in the conventional reduced resolution look-up table which is devised to process the gamut mapping in real time. Based on the tetrahedral interpolation, a new type hardware architecture for real-time gamut mapping is proposed in this paper. The proposed hardware architecture shows better processing speed and reduces the hardware cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2380-2388
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• 2015

A hardware implementation of MOD(moving object detection) algorithm using EGML(effective Gaussian mixture learning)- based background subtraction to detect moving objects in video is described. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is adopted to improve operating speed. The MOD processor designed in Verilog-HDL has been verified by FPGA-in-the-loop verification using MATLAB/Simulink. The MOD processor has 2,218 slices on the Virtex5-XC5VSX95T FPGA device and its throughput is 102 MSamples/s at 102 MHz clock frequency. Evaluation results of the MOD processor for 12 images in the IEEE CDW-2012 dataset show that the average recall value is 0.7631, the average precision value is 0.7778 and the average F-measure value is 0.7535.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.842-845
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• 2008

This paper propose a dormitory management system based on 13.56MHz RFID system. The proposed dormitory management system consists of three parts, the RFID hardware system the middleware, and the application. RFID hardware system uses 13.56MHz frequency which is suitable for a close range. The middleware is implemented to accept the RFID hardware system values using RS-232c communication method and forward the values to the application. The application is designed to make the DB using the forwarded values, and works based on the DB. The efficacy of the proposed dormitory management system is verified by means of experiments. In the experiments, we set up the system to the dormitory of Daeduk College to show the improvement results of proposed system.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.