• 한국정보통신학회논문지
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• 제25권1호
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• pp.20-26
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• 2021

오늘날의 시스템들은 더 빠른 실행 속도와 더 적은 전력 소모를 위해 하드웨어와 소프트웨어 요소를 함께 포함하고 있다. 기존 하드웨어 및 소프트웨어 공동 설계에서 소프트웨어와 하드웨어의 비율은 설계자의 경험적 지식에 의해 나뉘었다. 설계자들은 반복적으로 가속기와 응용 프로그램을 재구성하고 시뮬레이션하며 최적의 결과를 찾는다. 설계를 변경하며 반복적으로 시뮬레이션하는 것은 시간이 많이 소모되는 일이다. 본 논문에서는 에너지 효율적인 FPGA 가속기 설계를 위한 하드웨어 및 소프트웨어 공동 설계 플랫폼을 제안한다. 제안하는 플랫폼은 가속기를 구성하는 주요 성분을 변수화해 응용 프로그램 코드와 하드웨어 코드를 자동으로 생성하여 설계자가 적절한 하드웨어 비율을 쉽게 찾을 수 있도록 한다. 공동 설계 플랫폼은 Xilinx Alveo U200 FPGA가 탑재된 서버에서 Vitis 플랫폼을 기반으로 동작한다. 공동 설계 플랫폼을 통해 1000개의 행을 가지는 두 행렬의 곱셈 연산 가속기를 최적화한 결과 응용프로그램보다 실행 시간이 90.7%, 전력 소모가 56.3% 감소하였다.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1915-1920
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• 2015

ISO 26262 is an international standard for the functional safety of electric and electronic systems in vehicles, and this standard has become a major issue in the automotive industry. In this paper, a functional safety compliant electronic control unit (ECU) for an electric power steering (EPS) system and a demonstration purposed EPS system are developed, and a software and hardware structure for a safety critical system is presented. EPS is the most recently introduced power steering technology for vehicles, and it can improve driver’s convenience and fuel efficiency. In conformity with the design process specified in ISO 26262, the Automotive Safety Integrity Level (ASIL) of an EPS system is evaluated, and hardware and software are designed based on an asymmetric dual processing unit architecture and an external watchdog. The developed EPS system effectively demonstrates the fault detection and diagnostic functions of a functional safety compliant ECU as well as the basic EPS functions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.203-211
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• 2012

This paper proposes a $16{\times}16$ and $32{\times}32$ inverse transform architecture for HEVC (High Efficiency Video Coding). HEVC large transform of $16{\times}16$ and $32{\times}32$ suffers from huge computational complexity. To resolve this problem, we proposed a new large inverse transform architecture based on hardware reuse. The processing element is optimized by exploiting fully recursive and regular butterfly structure. To achieve low area, the processing element is implemented by shifters and adders without multiplier. Implementation of the proposed 2-D inverse transform architecture in 0.18 ${\mu}m$ technology shows about 300 MHz frequency and 287 Kgates area, which can process 4K ($3840{\times}2160$)@ 30 fps image.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.34-42
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• 2013

Human faces have been broadly studied in digital image and video processing fields. An appearance-based method, the adaptive boosting learning algorithm using integral image representations has been successfully employed for face detection, taking advantage of the feature extraction's low computational complexity. In this paper, we propose a face-detection postprocessing method that equalizes instantaneous facial regions in an efficient hardware architecture for use in real-time multimedia applications. The proposed system requires low hardware resources and exhibits robust performance in terms of the movements, zooming, and classification of faces. A series of experimental results obtained using video sequences collected under dynamic conditions are discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.2827-2829
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• 1999

Genetic algorithms were described as a method of solving large-scaled optimization problems with complex constraints. It has overcome their slowness, a major drawback of genetic algorithms using hardware implementation of genetic algorithm processor (GAP). In this study, we proposed GAP effectively connecting the goodness of survival-based GA, steady-state GA, tournament selection. Using Pipeline Parallel processing, handshaking protocol effectively, the proposed GAP exhibits 50% speed-up over survival-based GA which runs one million crossovers per second(1MHz). It will be used for high speed processing such of central processor of EHW, robot control and many optimization problem.

• Journal of Electrical Engineering and Technology
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• 제9권3호
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• pp.1072-1079
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• 2014

This paper introduces a coordinated droop control for the stand-alone DC micro-grid, which is composed of photo-voltaic generator, wind power generator, engine generator, and battery storage with SOC (state of charge) management system. The operation of stand-alone DC micro-grid with the coordinated droop control was analyzed with computer simulation. Based on simulation results, a hardware simulator was built and tested to analyze the performance of proposed system. The developed simulation model and hardware simulator can be utilized to design the actual stand-alone DC micro-grid and to analyze its performance. The coordinated droop control can improve the reliability and efficiency of the stand-alone DC micro-grid.

• 한국군사과학기술학회지
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• 제13권5호
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• pp.785-792
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• 2010

This paper on the Research of Naval Electronic Warfare System HILS(Hardware In the Loop System) describes the EW engagement HILS construction method for evaluation of the operational concept analysis on active RF Decoy in staying in the air and the deceit ability to anti-ship missile seeker. We obtain the EW M&S technology of EW engagement HILS and EW efficiency analysis from this project. This Naval Electronic Warfare System HILS technology will support Active Decoy Development Project and any other HILS of EW weapon in KOREA ARMY/NAVY/AIR FORCE.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.615-618
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• 2000

A number of studies have recently been made on hardware for a biological neuron f3r application with information processing functions of neural networks. We have been trying to produce hardware from the viewpoint that development of a new hardware neuron model is one of the important problems in the study of neural networks. In this paper, we first discuss the circuit structure of a pulse-type hardware neuron model with the enhancement-mode MOSFETs (E-MOSFETs). And we construct a pulse-type hardware neuron model using I-MOSFETs. As a result, it is shown that our proposed new model can exhibit firing phenomena even if the power supply voltage becomes less than 1.5[V]. So it is verified that our model is profitable for IC.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.473-476
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• 2004

Low-Density Parity-Check (LDPC) codes are recently emerged due to its excellent performance to use. However, the parity check matrices (H) of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix for partially parallel decoder structures, which is efficient in hardware implementation of both decoders and encoders. Using proposed methods, the encoding design can become practical while keeping the hardware complexity of partially parallel decoder structures.

• 한국정보전자통신기술학회논문지
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• 제7권3호
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• pp.121-125
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• 2014

DSP 시스템에서 널리 사용되는 힐버트 변환에서 곱셈 연산은 반드시 필요한 요소이며 변환에 사용되는 계수의 차수가 높아질수록 하드웨어는 복잡하고 많은 양의 게이트를 필요로 한다. 본 연구에서는 힐버트 변환에 사용되는 곱셈연산에 MAG 알고리즘이 적용된 쉬프트와 덧셈을 사용한 곱셈블록을 구현하여 하드웨어의 복잡도를 줄일 수 있다.