• ETRI Journal
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• 제29권4호
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• pp.530-532
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• 2007

This paper presents a simple method to implement a complete on-line portable wireless holter including an electrocardiogram (ECG) monitoring, processing, and communication protocol. The proposed algorithm significantly reduces the hardware resources of threshold estimation for ECG compression, using the standard deviation updated with each new input signal sample. The new method achieves superior performance in terms of hardware complexity, channel occupation and memory requirements, while keeping the ECG quality at a clinically acceptable level.

• 전기전자학회논문지
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• 제18권3호
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• pp.356-361
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• 2014

This paper proposes hardware architecture of HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) binarizer. The proposed binarizer was designed and implemented as an independent module that can be integrated into HEVC CABAC encoder. It generates each bin string of each syntax element in a single cycle. It consists of controller module, TU (truncated unary binarization) module, TR (truncated Rice binarization) module, FL (fixed length binarization) module, EGK (k-th order exp-Golomb coding) module, CALR (coeff_abs_level_remaining) module, QP Delta (cu_qp_delta_abs) module, Intra Pred (intra_chroma_pred_mode) module, Inter Pred (inter_pred_idc) module, and Part Mode (part_mode) module. The proposed binarizer was designed in Verilog HDL, and it was implemented in 45 nm technology. Its operating speed, gate count, and power consumption are 200 MHz, 1,678 gates, and 50 uW, respectively.

• 한국통신학회논문지
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• 제41권11호
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• pp.1502-1506
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• 2016

HEVC (High Efficiency Video Coding)는 최근에 제안된 비디오 압축 표준으로서 이전의 비디오 압축 표준보다 두 배 이상의 부호화 효율을 가진다. 다양한 종류의 인트라 예측 블록과 모드는 HEVC의 높은 압축 성능과 연산 복잡도 증가의 주요 요인이다. 본 논문은 파이프라인과 인터리빙 기술을 사용하여 하드웨어 자원의 요구조건을 줄이는 반면 효율과 성능은 향상시킨 HEVC 용 인트라 예측 하드웨어 구조를 제시한다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제4권1호
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• pp.7-11
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• 2004

This paper proposes a new immunotronic approach for the fault detection in hardware. The suggested method is, inspired by biology and its implementation is based on genetic algorithm. Tolerance conditions in the immunotronic system for fault detection correspond to the antibodies in the biological immune system. A novel algorithm of generating tolerance conditions is suggested based on the principle of the antibody diversity and GA optimization is employed to select mature tolerance conditions in immunotronic fault detection system. The suggested method is applied to the fault detection for MCNC benchmark FSMs (finite state machines) and its effectiveness is demonstrated by the computer simulation.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.485-490
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• 1992

This paper describes a hardware structure and a communication system of a multiple autonomous robots system. Many studies have been devoted to the development of a single autonomous robot. It is, however, also necessary to investigate decentralized multiple autonomous robots system in order to make wider use of such robots. We have been studying a multiple autonomous robots system employing two mobile robots. In this paper, problems are overviewed on the developed multiple autonomous robots system from the viewpoint of hardware and communication, and an improved system is presented, which employs a new control strategy of a mobile robot and realizes reliable data communication between host computers.

• Transactions on Electrical and Electronic Materials
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• 제18권6호
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• pp.320-322
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• 2017

In this paper, a high-performance, low-area gradient-magnitude calculator architecture is proposed, based on approximate image processing. To reduce the computational complexity of the gradient-magnitude calculation, vector properties, the symmetry axis, and common terms were applied in a hardware-resource-shared architec-ture. The proposed gradient-magnitude calculator was implemented using an Altera Cyclone IV FPGA (EP4CE115F29) and the Quartus II v.16 device software. It satisfied the output-data quality while reducing the logic elements by 23% and the embedded multipliers by 76%, compared with previous work.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.781-782
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• 2006

This treatise proposed environment for Embedded system's development. Virtual platform can help to solve problem that hardware designer can experience at design process of hardware. Compose circuit of most suitable that is verified before mix parts by various kinds method and compose circuit by board level because can do simulation with software and software that is optimized to hardware and offer flexibility that can test. Therefore, can shorten expense that is cost in development and time. Embody development platform for 8051 systems for verification of development platform, and compose and verified system in various kinds structure.

• 한국정보전자통신기술학회논문지
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• 제11권5호
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• Journal of Semiconductor Engineering
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• 제2권3호
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• pp.142-153
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• 2021

Recent research on synaptic devices has been reviewed from the perspective of hardware-based neuromorphic computing. In addition, the backgrounds of neuromorphic computing and two training methods for hardware-based neuromorphic computing are described in detail. Moreover, two types of memristor- and CMOS-based synaptic devices were compared in terms of both the required performance metrics and low-power applications. Based on a review of recent studies, additional power-scalable synaptic devices such as tunnel field-effect transistors are suggested for a plausible candidate for neuromorphic applications.

• 한국멀티미디어학회논문지
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• 제20권2호
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• pp.289-297
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• 2017

When implementing a hardware elliptic curve cryptosystem (ECC) module, the efficient design of Modular Inverse (MI) algorithm is especially important since it requires much more computation than other finite field operations in ECC. Among the MI algorithms, binary Right-Shift modular inverse (RS) algorithm has good performance when implemented in hardware, but Montgomery Modular Inverse (MMI) algorithm is not considered in [1, 2]. Since MMI has a similar structure to that of RS, we show that the area-improvement idea that is applied to RS is applicable to MMI, and that we can improve the speed of MMI. We designed area- and speed-improved MMI variants as hardware modules and analyzed their performance.