• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.95-98
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• 2004

In this paper, the hardware design of a transmission convergence sublayer(TC) for boradband wireless access system is described, which performs (1) formatting TC PDUs to MAC PDUs, (2) RS encoding/decoding, (3) providing various control signal to PHY modem. The TC hardware has been designed in VHDL, and successfully synthesized in an FPGA chip.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.448-451
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• 2003

For this research, we developed the hardware and software of the measurement system for on-line test and evaluation. The software controls the hardware of the measurement data and acts as interface between users and the system hardware. In this paper, we is studied for temperature measurement of main transformer. In order to this test is developed measurement system. Using this system, we obtained important result for main transformer temperature.

• 전기전자학회논문지
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• 제25권1호
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• pp.10-14
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• 2021

본 논문에서는 기존 CIE1931 색 좌표계를 이용한 색상 보정 연산의 복잡성을 개선한 하드웨어를 제안한다. 기존 알고리즘은 연산 과정에서 큰 비트 수를 계산하기 위해 사용되는 4-Split Multiply 연산으로 인해 하드웨어가 커지는 단점이 있다. 제안하는 알고리즘은 기존 알고리즘의 정의된 R2X, X2R 연산을 미리 계산하여 하나의 행렬로 만들어 영상에 적용함으로써 연산량 감소와 하드웨어 크기 감소가 가능하다. Verilog로 설계된 하드웨어의 Xilinx 합성 결과를 비교함으로써 하드웨어 자원 감소와 4K 환경 실시간 처리를 위한 성능을 확인할 수 있다. 또한, FPGA 보드에서의 실행 결과를 제시함으로써 하드웨어 탑재 동작을 검증하였다.

• 전기전자학회논문지
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• 제18권4호
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• pp.630-635
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• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• Journal of Power Electronics
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• 제6권2호
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

• International journal of advanced smart convergence
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• 제9권4호
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• pp.62-73
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• 2020

In this paper, we present electronic acupuncture needles we have developed using intelligence technology based on Bluetooth in order to allow anyone to simply receive customized remote diagnosis and treatment by clicking on the menu of the smartphone regardless of time and place. In order to determine the health condition and disease of patients, we have developed a software and a hardware of electronic acupuncture needles, operating on Bluetooth which transmits biometric data to oriental medical doctors using the functions of automatically determining pulse diagnosis, tongue diagnosis, and oxygen saturation; the functions are most commonly used in herbal treatment. In addition, using fuzzy logic and reasoning based on smartphones, we present in this paper an algorithm and the results of completion of hardware implementation for electronic acupuncture needles, appropriate for the body conditions of patients; the algorithm and the hardware implementation are for a treatment time duration by electronic acupuncture needles, an automatic determinations of pulse diagnosis, tongue diagnosis, and oxygen saturation, a function implementation for automatic display of acupuncture point, and a strength adjustment of electronic acupuncture needles. As a result of our simulation, we have shown that the treatment of patients, performed using an Electronic Acupuncture Needles based on intelligence, is more efficient compared to the treatment that was performed before.

• 전기학회논문지
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• 제66권9호
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• pp.1373-1378
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• 2017

This paper presents a basic ECU(Electronic Control Unit) hardware development procedure for the functional safety of in-vehicle network systems. We consider complete hardware redundancy as a safety mechanism for in-vehicle communication network under the assumption of the wired network failure such as disconnection of a CAN bus. An ESC (Electronic Stability Control) system is selected as an item and the required ASIL(Automotive Safety Integrity Level) for this item is assigned by performing the HARA(Hazard Analysis and Risk Assessment). The basic hardware architecture of the ESC system is designed with a microcontroller, passive components, and communication transceivers. The required ASIL for ESC system is shown to be satisfied with the designed safety mechanism by calculation of hardware architecture metrics such as the SPFM(Single Point Fault Metric) and the LFM(Latent Fault Metric).

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.112-115
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• 2008

본 논문에서는 AMBA 기반으로 사용될 수 있는 H.264용 High Profile IP를 제안한다. 설계된 모듈은 한 매크로 블록 당 최대 306 cycle내에 동작한다. 제안된 Encoder 구조를 검증하기 위하여 JM 13.2부터 reference C를 개발하였으며, reference C로부터 test vector를 추출하여 설계 된 회로를 검증하였다. 우리는 Hardware cost를 줄이기 위하여 plan mode를 제거하였고, SAD 계산 방법을 사용하여 Hardware cost와 cycle을 줄이는 방법을 채택하였다. 제안된 회로는 133MHz clock에서 동작하며, 합성결과 TSMC 0.18um 공정에 램 포함 25만 gate크기이다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권12호
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 추계종합학술대회
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• pp.119-122
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• 2007

본 논문에서는 모바일 폰 카메라의 프레임 단위 영상 신호 처리 과정에서 필요한 나눗셈 연산을 위한 나눗셈기 설계 방법을 제안한다. 나눗셈기의 내부 데이터 처리 방법에는 직렬 방식과 병렬 방식이 있다. 직렬방식은 실시간 연산이 가능한 반면에 많은 비교기와 Buffer Memory의 사용으로 인해 하드웨어 사이즈가 크다. 병렬방식은 실시간 연산을 할 수 없지만 하나의 비교기를 공유해서 연산함으로 직렬방식에 비해 하드웨어 크기를 줄일 수 있다. 이미지 처리를 위한 프레임 단위 연산은 실시간 연산을 필요로 하지 않으므로 하드웨어 자원으 효율성을 위해 직렬방식 나눗셈기를 적용한다. 입출력 조건을 동일하게 해서 병렬방식과 직렬방식의 나눗셈을 구현하여 하드웨어 크기를 비교 했을 때 동일한 동작 주파수에서 직렬방식의 나눗셈기가 병렬방식의 나눗셈기의 대락 1/8 정도의 하드웨어 크기를 가지는 것을 확인하였다.